-2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
-
- * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
- stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
- ARM_EXT_V8.
- (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
-
-2015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
-
-opcodes/
- * rx-decode.opc (movco): Use uniqe id.
- (movli): Likewise.
- (stnz): Condition fix.
- (mvtacgu): Destination fix.
- * rx-decode.c: Regenerate.
-
-2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
-
- * rx-deocde.opc: Add new instructions pattern.
- * rx-deocde.c: Regenerate.
- * rx-dis.c (register_name): Add new register.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_SSHIFT_H): New.
- (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
- and fcvtzu to the Adv.SIMD scalar shift by immediate group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_VSHIFT_H): New.
- (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
- and fcvtzu to the Adv.SIMD shift by immediate group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_SISD_PAIR_H): New.
- (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
- fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
-
- * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
- and adjust calculation to ignore qualifier for type 2H.
- * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_SIMD_IMM_H): New.
- (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
- modified immediate group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_XLANES_FP_H): New.
- (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
- fminnmv, fminv to the Adv.SIMD across lanes group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
- fmls, fmul and fmulx to the scalar indexed element group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
- (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
- fmulx to the vector indexed element group.
+2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
- (QL_S_2SAMEH): New.
- (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
- fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
- frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
- fcvtzu and frsqrte to the scalar two register misc. group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_V2SAMEH): New.
- (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
- fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
- frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
- fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
- and fsqrt to the vector register misc. group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
- fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
- to the scalar three same group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_V3SAMEH): New.
- (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
- fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
- fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
- fcmgt, facgt and fminp to the vector three same group.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-tbl.h (aarch64_feature_simd_f16): New.
- (SIMD_F16): New.
-
-2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
- removed statement.
- (aarch64_pstatefield_supported_p): Move feature checks for AT
- registers ..
- (aarch64_sys_ins_reg_supported_p): .. to here.
-
-2015-12-12 Alan Modra <amodra@gmail.com>
-
- PR 19359
- * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
- (powerpc_opcodes): Remove single-operand mfcr.
-
-2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm.c (aarch64_ins_hint): New.
- * aarch64-asm.h (aarch64_ins_hint): Declare.
- * aarch64-dis.c (aarch64_ext_hint): New.
- * aarch64-dis.h (aarch64_ext_hint): Declare.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-opc.c (aarch64_hint_options): New.
- * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
-
-2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
-
-2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
- pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
- pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
- pmscr_el2.
- (aarch64_sys_reg_supported_p): Add architecture feature tests for
- the new registers.
-
-2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
- (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
- feature test for "s1e1rp" and "s1e1wp".
-
-2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
- (aarch64_sys_ins_reg_supported_p): New.
-
-2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
- with aarch64_sys_ins_reg_has_xt.
- (aarch64_ext_sysins_op): Likewise.
- * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
- (F_HASXT): New.
- (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
- (aarch64_sys_regs_dc): Likewise.
- (aarch64_sys_regs_at): Likewise.
- (aarch64_sys_regs_tlbi): Likewise.
- (aarch64_sys_ins_reg_has_xt): New.
-
-2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add "uao".
- (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
- (aarch64_pstatefields): Add "uao".
- (aarch64_pstatefield_supported_p): Add checks for "uao".
-
-2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
- "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
- "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
- (aarch64_sys_reg_supported_p): Add architecture feature tests for
- new registers.
-
-2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-tbl.h (aarch64_feature_ras): New.
- (RAS): New.
- (aarch64_opcode_table): Add "esb".
-
-2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
+ PR binutis/18386
+ * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
+ (indir_v_mode): New.
+ Add comments for '&'.
+ (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
+ (putop): Handle '&'.
+ (intel_operand_size): Handle indir_v_mode.
+ (OP_E_register): Likewise.
+ * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
+ 64-bit indirect call/jmp for AMD64.
+ * i386-tbl.h: Regenerated
+
+2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (struct arc_operand_iterator): New structure.
+ (find_format_from_table): All the old content from find_format,
+ with some minor adjustments, and parameter renaming.
+ (find_format_long_instructions): New function.
+ (find_format): Rewritten.
+ (arc_insn_length): Add LSB parameter.
+ (extract_operand_value): New function.
+ (operand_iterator_next): New function.
+ (print_insn_arc): Use new functions to find opcode, and iterator
+ over operands.
+ * arc-opc.c (insert_nps_3bit_dst_short): New function.
+ (extract_nps_3bit_dst_short): New function.
+ (insert_nps_3bit_src2_short): New function.
+ (extract_nps_3bit_src2_short): New function.
+ (insert_nps_bitop1_size): New function.
+ (extract_nps_bitop1_size): New function.
+ (insert_nps_bitop2_size): New function.
+ (extract_nps_bitop2_size): New function.
+ (insert_nps_bitop_mod4_msb): New function.
+ (extract_nps_bitop_mod4_msb): New function.
+ (insert_nps_bitop_mod4_lsb): New function.
+ (extract_nps_bitop_mod4_lsb): New function.
+ (insert_nps_bitop_dst_pos3_pos4): New function.
+ (extract_nps_bitop_dst_pos3_pos4): New function.
+ (insert_nps_bitop_ins_ext): New function.
+ (extract_nps_bitop_ins_ext): New function.
+ (arc_operands): Add new operands.
+ (arc_long_opcodes): New global array.
+ (arc_num_long_opcodes): New global.
+ * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
+
+2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * nds32-asm.h: Add extern "C".
+ * sh-opc.h: Likewise.
+
+2016-06-01 Graham Markall <graham.markall@embecosm.com>
+
+ * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
+ 0,b,limm to the rflt instruction.
+
+2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
+ constant.
+
+2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/20145
+ * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
+ CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
+ CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
+ CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
+ CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
+ * i386-init.h: Regenerated.
- * i386-dis.c (MOD_0F01_REG_5): New.
- (RM_0F01_REG_5): Likewise.
- (reg_table): Use MOD_0F01_REG_5.
- (mod_table): Add MOD_0F01_REG_5.
- (rm_table): Add RM_0F01_REG_5.
- * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
- (cpu_flags): Add CpuOSPKE.
- * i386-opc.h (CpuOSPKE): New.
- (i386_cpu_flags): Add cpuospke.
- * i386-opc.tbl: Add rdpkru and wrpkru instructions.
+2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/20145
+ * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
+ CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
+ CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
+ Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
+ CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
+ CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
+ CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
+ Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
+ CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
+ CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
+ CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
+ for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
+ CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
+ CpuRegMask for AVX512.
+ (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
+ and CpuRegMask.
+ (set_bitfield_from_cpu_flag_init): New function.
+ (set_bitfield): Remove const on f. Call
+ set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
+ * i386-opc.h (CpuRegMMX): New.
+ (CpuRegXMM): Likewise.
+ (CpuRegYMM): Likewise.
+ (CpuRegZMM): Likewise.
+ (CpuRegMask): Likewise.
+ (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
+ and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
-2015-12-07 DJ Delorie <dj@redhat.com>
-
- * rl78-decode.opc: Enable MULU for all ISAs.
- * rl78-decode.c: Regenerate.
-
-2015-12-07 Alan Modra <amodra@gmail.com>
-
- * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
- major opcode/xop.
-
-2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (special_flag_p): Match full mnemonic.
- * arc-opc.c (print_insn_arc): Check section size to read
- appropriate number of bytes. Fix printing.
- * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
- arguments.
-
-2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
- <ldah>: ... to this.
-
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
- (QL_INT2FP_H, QL_FP2INT_H): New.
- (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
- (QL_DST_H): New.
- (QL_FCCMP_H): New.
- (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
- fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
- fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
- fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
- frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
- fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
- fcsel.
-
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-opc.c (half_conv_t): New.
- (expand_fp_imm): Replace is_dp flag with the parameter size to
- specify the number of bytes for the required expansion. Treat
- a 16-bit expansion like a 32-bit expansion. Add check for an
- unsupported size request. Update comment.
- (aarch64_print_operand): Update to support 16-bit floating point
- values. Update for changes to expand_fp_imm.
-
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
-
- * aarch64-tbl.h (aarch64_feature_fp_f16): New.
- (FP_F16): New.
-
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
- "rev64".
+ PR gas/20154
+ * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
+ (opcode_modifiers): Add AMD64 and Intel64.
+ (main): Properly verify CpuMax.
+ * i386-opc.h (CpuAMD64): Removed.
+ (CpuIntel64): Likewise.
+ (CpuMax): Set to CpuNo64.
+ (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
+ (AMD64): New.
+ (Intel64): Likewise.
+ (i386_opcode_modifier): Add amd64 and intel64.
+ (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
+ on call and jmp.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
- * aarch64-asm-2.c: Regenerate.
- * aarch64-asm.c (convert_bfc_to_bfm): New.
- (convert_to_real): Add case for OP_BFC.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-dis.c: (convert_bfm_to_bfc): New.
- (convert_to_alias): Add case for OP_BFC.
- * aarch64-opc-2.c: Regenerate.
- * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
- to allow width operand in three-operand instructions.
- * aarch64-tbl.h (QL_BF1): New.
- (aarch64_feature_v8_2): New.
- (ARMV8_2): New.
- (aarch64_opcode_table): Add "bfc".
+ PR gas/20154
+ * i386-gen.c (main): Fail if CpuMax is incorrect.
+ * i386-opc.h (CpuMax): Set to CpuIntel64.
+ * i386-tbl.h: Regenerated.
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+2016-05-27 Nick Clifton <nickc@redhat.com>
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-dis.c: Weaken assert.
- * aarch64-gen.c: Include the instruction in the list of its
- possible aliases.
+ PR target/20150
+ * msp430-dis.c (msp430dis_read_two_bytes): New function.
+ (msp430dis_opcode_unsigned): New function.
+ (msp430dis_opcode_signed): New function.
+ (msp430_singleoperand): Use the new opcode reading functions.
+ Only disassenmble bytes if they were successfully read.
+ (msp430_doubleoperand): Likewise.
+ (msp430_branchinstr): Likewise.
+ (msp430x_callx_instr): Likewise.
+ (print_insn_msp430): Check that it is safe to read bytes before
+ attempting disassembly. Use the new opcode reading functions.
-2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
- * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
- (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
- feature test.
+ * ppc-opc.c (CY): New define. Document it.
+ (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
-2015-11-23 Tristan Gingold <gingold@adacore.com>
+2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
- * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
+ * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
+ CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
+ and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
+ CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
+ CPU_ANY_AVX_FLAGS.
+ * i386-init.h: Regenerated.
-2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
+2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
- * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
- sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
- tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
- amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
- cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
- cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
- cnthv_ctl_el2, cnthv_cval_el2.
- (aarch64_sys_reg_supported_p): Update for the new system
- registers.
+ PR gas/20141
+ * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
+ CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
+ * i386-init.h: Regenerated.
-2015-11-20 Nick Clifton <nickc@redhat.com>
+2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
- PR binutils/19224
- * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
+ * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
+ CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
+ * i386-init.h: Regenerated.
-2015-11-20 Nick Clifton <nickc@redhat.com>
+2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
- * po/zh_CN.po: Updated simplified Chinese translation.
+ * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
+ information.
+ (print_insn_arc): Set insn_type information.
+ * arc-opc.c (C_CC): Add F_CLASS_COND.
+ * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
+ (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
+ (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
+ (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
+ (brne, brne_s, jeq_s, jne_s): Likewise.
-2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
+2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
- * aarch64-opc.c (operand_general_constraint_met_p): Check validity
- of MSR PAN immediate operand.
+ * arc-tbl.h (neg): New instruction variant.
-2015-11-16 Nick Clifton <nickc@redhat.com>
+2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
- * rx-dis.c (condition_names): Replace always and never with
- invalid, since the always/never conditions can never be legal.
+ * arc-dis.c (find_format, find_format, get_auxreg)
+ (print_insn_arc): Changed.
+ * arc-ext.h (INSERT_XOP): Likewise.
-2015-11-13 Tristan Gingold <gingold@adacore.com>
+2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
- * configure: Regenerate.
+ * tic54x-dis.c (sprint_mmr): Adjust.
+ * tic54x-opc.c: Likewise.
-2015-11-11 Alan Modra <amodra@gmail.com>
- Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
- Add PPC_OPCODE_VSX3 to the vsx entry.
- (powerpc_init_dialect): Set default dialect to power9.
- * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
- insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
- extract_l1 insert_xtq6, extract_xtq6): New static functions.
- (insert_esync): Test for illegal L operand value.
- (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
- XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
- XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
- XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
- PPCVSX3): New defines.
- (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
- fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
- <mcrxr>: Use XBFRARB_MASK.
- <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
- bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
- cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
- cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
- lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
- lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
- modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
- rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
- stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
- subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
- vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
- vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
- vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
- vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
- vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
- vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
- vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
- xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
- xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
- xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
- xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
- xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
- xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
- xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
- xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
- xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
- xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
- xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
- xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
- xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
- <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
- <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
-
-2015-11-02 Nick Clifton <nickc@redhat.com>
-
- * rx-decode.opc (rx_decode_opcode): Decode extra NOP
- instructions.
- * rx-decode.c: Regenerate.
+2016-05-19 Alan Modra <amodra@gmail.com>
-2015-11-02 Nick Clifton <nickc@redhat.com>
+ * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
- * rx-decode.opc (rx_disp): If the displacement is zero, set the
- type to RX_Operand_Zero_Indirect.
- * rx-decode.c: Regenerate.
- * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
+2016-05-19 Alan Modra <amodra@gmail.com>
-2015-10-28 Yao Qi <yao.qi@linaro.org>
+ * ppc-opc.c: Formatting.
+ (NSISIGNOPT): Define.
+ (powerpc_opcodes <subis>): Use NSISIGNOPT.
- * aarch64-dis.c (aarch64_decode_insn): Add one argument
- noaliases_p. Update comments. Pass noaliases_p rather than
- no_aliases to aarch64_opcode_decode.
- (print_insn_aarch64_word): Pass no_aliases to
- aarch64_decode_insn.
+2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
-2015-10-27 Vinay <Vinay.G@kpit.com>
+ * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
+ replacing references to `micromips_ase' throughout.
+ (_print_insn_mips): Don't use file-level microMIPS annotation to
+ determine the disassembly mode with the symbol table.
- PR binutils/19159
- * rl78-decode.opc (MOV): Added offset to DE register in index
- addressing mode.
- * rl78-decode.c: Regenerate.
+2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
-2015-10-27 Vinay Kumar <vinay.g@kpit.com>
+ * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
- PR binutils/19158
- * rl78-decode.opc: Add 's' print operator to instructions that
- access system registers.
- * rl78-decode.c: Regenerate.
- * rl78-dis.c (print_insn_rl78_common): Decode all system
- registers.
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
-2015-10-27 Vinay Kumar <vinay.g@kpit.com>
+ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
+ mips64r6.
+ * mips-opc.c (D34): New macro.
+ (mips_builtin_opcodes): Define bposge32c for DSPr3.
- PR binutils/19157
- * rl78-decode.opc: Add 'a' print operator to mov instructions
- using stack pointer plus index addressing.
- * rl78-decode.c: Regenerate.
+2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
-2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+ * i386-dis.c (prefix_table): Add RDPID instruction.
+ * i386-gen.c (cpu_flag_init): Add RDPID flag.
+ (cpu_flags): Add RDPID bitfield.
+ * i386-opc.h (enum): Add RDPID element.
+ (i386_cpu_flags): Add RDPID field.
+ * i386-opc.tbl: Add RDPID instruction.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Regenerate.
- * s390-opc.c: Fix comment.
- * s390-opc.txt: Change instruction type for troo, trot, trto, and
- trtt to RRF_U0RER since the second parameter does not need to be a
- register pair.
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
-2015-10-08 Nick Clifton <nickc@redhat.com>
+ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
+ branch type of a symbol.
+ (print_insn): Likewise.
- * arc-dis.c (print_insn_arc): Initiallise insn array.
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
-2015-10-07 Yao Qi <yao.qi@linaro.org>
+ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
+ Mainline Security Extensions instructions.
+ (thumb_opcodes): Add entries for narrow ARMv8-M Security
+ Extensions instructions.
+ (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
+ instructions.
+ (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
+ special registers.
+
+2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
+
+2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
+ (arcExtMap_genOpcode): Likewise.
+ * arc-opc.c (arg_32bit_rc): Define new variable.
+ (arg_32bit_u6): Likewise.
+ (arg_32bit_limm): Likewise.
+
+2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-gen.c (VERIFIER): Define.
+ * aarch64-opc.c (VERIFIER): Define.
+ (verify_ldpsw): Use static linkage.
+ * aarch64-opc.h (verify_ldpsw): Remove.
+ * aarch64-tbl.h: Use VERIFIER for verifiers.
+
+2016-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR target/19722
+ * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
+ * aarch64-opc.c (verify_ldpsw): New function.
+ * aarch64-opc.h (verify_ldpsw): New prototype.
+ * aarch64-tbl.h: Add initialiser for verifier field.
+ (LDPSW): Set verifier to verify_ldpsw.
+
+2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/19983
+ PR binutils/19984
+ * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
+ smaller than address size.
+
+2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * alpha-dis.c: Regenerate.
+ * crx-dis.c: Likewise.
+ * disassemble.c: Likewise.
+ * epiphany-opc.c: Likewise.
+ * fr30-opc.c: Likewise.
+ * frv-opc.c: Likewise.
+ * ip2k-opc.c: Likewise.
+ * iq2000-opc.c: Likewise.
+ * lm32-opc.c: Likewise.
+ * lm32-opinst.c: Likewise.
+ * m32c-opc.c: Likewise.
+ * m32r-opc.c: Likewise.
+ * m32r-opinst.c: Likewise.
+ * mep-opc.c: Likewise.
+ * mt-opc.c: Likewise.
+ * or1k-opc.c: Likewise.
+ * or1k-opinst.c: Likewise.
+ * tic80-opc.c: Likewise.
+ * xc16x-opc.c: Likewise.
+ * xstormy16-opc.c: Likewise.
+
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
+ fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
+ calcsd, and calcxd instructions.
+ * arc-opc.c (insert_nps_bitop_size): Delete.
+ (extract_nps_bitop_size): Delete.
+ (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
+ (extract_nps_qcmp_m3): Define.
+ (extract_nps_qcmp_m2): Define.
+ (extract_nps_qcmp_m1): Define.
+ (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
+ (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
+ (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
+ NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
+ NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
+ NPS_QCMP_M3.
+
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
+
+2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.in: Regenerated with automake 1.11.6.
+ * aclocal.m4: Likewise.
+
+2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
+ instructions.
+ * arc-opc.c (insert_nps_cmem_uimm16): New function.
+ (extract_nps_cmem_uimm16): New function.
+ (arc_operands): Add NPS_XLDST_UIMM16 operand.
+
+2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (arc_insn_length): New function.
+ (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
+ (find_format): Change insnLen parameter to unsigned.
+
+2016-04-13 Nick Clifton <nickc@redhat.com>
+
+ PR target/19937
+ * v850-opc.c (v850_opcodes): Correct masks for long versions of
+ the LD.B and LD.BU instructions.
+
+2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (find_format): Check for extension flags.
+ (print_flags): New function.
+ (print_insn_arc): Update for .extCondCode, .extCoreRegister and
+ .extAuxRegister.
+ * arc-ext.c (arcExtMap_coreRegName): Use
+ LAST_EXTENSION_CORE_REGISTER.
+ (arcExtMap_coreReadWrite): Likewise.
+ (dump_ARC_extmap): Update printing.
+ * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
+ (arc_aux_regs): Add cpu field.
+ * arc-regs.h: Add cpu field, lower case name aux registers.
- * aarch64-dis.c (aarch64_ext_sysins_op): Access field
- 'name' rather than 'template'.
- * aarch64-opc.c (aarch64_print_operand): Likewise.
+2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h: Add rtsc, sleep with no arguments.
+
+2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
+ Initialize.
+ (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
+ (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
+ (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
+ (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
+ (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
+ (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
+ (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
+ (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
+ (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
+ (arc_opcode arc_opcodes): Null terminate the array.
+ (arc_num_opcodes): Remove.
+ * arc-ext.h (INSERT_XOP): Define.
+ (extInstruction_t): Likewise.
+ (arcExtMap_instName): Delete.
+ (arcExtMap_insn): New function.
+ (arcExtMap_genOpcode): Likewise.
+ * arc-ext.c (ExtInstruction): Remove.
+ (create_map): Zero initialize instruction fields.
+ (arcExtMap_instName): Remove.
+ (arcExtMap_insn): New function.
+ (dump_ARC_extmap): More info while debuging.
+ (arcExtMap_genOpcode): New function.
+ * arc-dis.c (find_format): New function.
+ (print_insn_arc): Use find_format.
+ (arc_get_disassembler): Enable dump_ARC_extmap only when
+ debugging.
-2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
+2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
- * arc-dis.c: Revamped file for ARC support
- * arc-dis.h: Likewise.
- * arc-ext.c: Likewise.
- * arc-ext.h: Likewise.
- * arc-opc.c: Likewise.
- * arc-fxi.h: New file.
- * arc-regs.h: Likewise.
- * arc-tbl.h: Likewise.
+ * mips-dis.c (print_mips16_insn_arg): Mask unused extended
+ instruction bits out.
-2015-10-02 Yao Qi <yao.qi@linaro.org>
+2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
- * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
- argument insn type to aarch64_insn. Rename to ...
- (aarch64_decode_insn): ... it.
- (print_insn_aarch64_word): Caller updated.
+ * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
+ * arc-opc.c (arc_flag_operands): Add new flags.
+ (arc_flag_classes): Add new classes.
-2015-10-02 Yao Qi <yao.qi@linaro.org>
+2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
- * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
- (print_insn_aarch64_word): Caller updated.
+ * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
-2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
+2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
- * s390-mkopc.c (main): Parse htm and vx flag.
- * s390-opc.txt: Mark instructions from the hardware transactional
- memory and vector facilities with the "htm"/"vx" flag.
+ * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
+ encode1, rflt, crc16, and crc32 instructions.
+ * arc-opc.c (arc_flag_operands): Add F_NPS_R.
+ (arc_flag_classes): Add C_NPS_R.
+ (insert_nps_bitop_size_2b): New function.
+ (extract_nps_bitop_size_2b): Likewise.
+ (insert_nps_bitop_uimm8): Likewise.
+ (extract_nps_bitop_uimm8): Likewise.
+ (arc_operands): Add new operand entries.
-2015-09-28 Nick Clifton <nickc@redhat.com>
+2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
- * po/de.po: Updated German translation.
+ * arc-regs.h: Add a new subclass field. Add double assist
+ accumulator register values.
+ * arc-tbl.h: Use DPA subclass to mark the double assist
+ instructions. Use DPX/SPX subclas to mark the FPX instructions.
+ * arc-opc.c (RSP): Define instead of SP.
+ (arc_aux_regs): Add the subclass field.
-2015-09-28 Tom Rix <tom@bumblecow.com>
+2016-04-05 Jiong Wang <jiong.wang@arm.com>
- * ppc-opc.c (PPC500): Mark some opcodes as invalid
+ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
-2015-09-23 Nick Clifton <nickc@redhat.com>
+2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
- * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
- function.
- * tic30-dis.c (print_branch): Likewise.
- * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
- value before left shifting.
- * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
- * hppa-dis.c (print_insn_hppa): Likewise.
- * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
- array.
- * msp430-dis.c (msp430_singleoperand): Likewise.
- (msp430_doubleoperand): Likewise.
- (print_insn_msp430): Likewise.
- * nds32-asm.c (parse_operand): Likewise.
- * sh-opc.h (MASK): Likewise.
- * v850-dis.c (get_operand_value): Likewise.
-
-2015-09-22 Nick Clifton <nickc@redhat.com>
-
- * rx-decode.opc (bwl): Use RX_Bad_Size.
- (sbwl): Likewise.
- (ubwl): Likewise. Rename to ubw.
- (uBWL): Rename to uBW.
- Replace all references to uBWL with uBW.
- * rx-decode.c: Regenerate.
- * rx-dis.c (size_names): Add entry for RX_Bad_Size.
- (opsize_names): Likewise.
- (print_insn_rx): Detect and report RX_Bad_Size.
-
-2015-09-22 Anton Blanchard <anton@samba.org>
-
- * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
-
-2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * sparc-dis.c (print_insn_sparc): Handle the privileged register
- %pmcdper.
-
-2015-08-24 Jan Stancek <jstancek@redhat.com>
-
- * i386-dis.c (print_insn): Fix decoding of three byte operands.
-
-2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
-
- PR binutils/18257
- * i386-dis.c: Use MOD_TABLE for most of mask instructions.
- (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
- MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
- MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
- MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
- MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
- MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
- MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
- MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
- MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
- MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
- MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
- MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
- MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
- MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
- MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
- MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
- MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
- MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
- MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
- MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
- MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
- MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
- MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
- MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
- MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
- MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
- MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
- MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
- MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
- MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
- (vex_w_table): Replace terminals with MOD_TABLE entries for
- most of mask instructions.
-
-2015-08-17 Alan Modra <amodra@gmail.com>
-
- * cgen.sh: Trim trailing space from cgen output.
- * ia64-gen.c (print_dependency_table): Don't generate trailing space.
- (print_dis_table): Likewise.
- * opc2c.c (dump_lines): Likewise.
- (orig_filename): Warning fix.
- * ia64-asmtab.c: Regenerate.
-
-2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * arm-dis.c (print_insn_arm): Disassembling for all targets V6
- and higher with ARM instruction set will now mark the 26-bit
- versions of teq,tst,cmn and cmp as UNPREDICTABLE.
- (arm_opcodes): Fix for unpredictable nop being recognized as a
- teq.
-
-2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
-
- * micromips-opc.c (micromips_opcodes): Re-order table so that move
- based on 'or' is first.
- * mips-opc.c (mips_builtin_opcodes): Ditto.
-
-2015-08-11 Nick Clifton <nickc@redhat.com>
-
- PR 18800
- * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
- instruction.
-
-2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
-
- * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
-
-2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
-
- * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
- * i386-init.h: Regenerated.
+ * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
+ NPS_R_SRC1.
-2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/13571
- * i386-dis.c (MOD_0FC3): New.
- (PREFIX_0FC3): Renamed to ...
- (PREFIX_MOD_0_0FC3): This.
- (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
- (prefix_table): Replace Ma with Ev on movntiS.
- (mod_table): Add MOD_0FC3.
-
-2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
-
- * configure: Regenerated.
-
-2015-07-23 Alan Modra <amodra@gmail.com>
-
- PR 18708
- * i386-dis.c (get64): Avoid signed integer overflow.
-
-2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
-
- PR binutils/18631
- * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
- "EXEvexHalfBcstXmmq" for the second operand.
- (EVEX_W_0F79_P_2): Likewise.
- (EVEX_W_0F7A_P_2): Likewise.
- (EVEX_W_0F7B_P_2): Likewise.
-
-2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
-
- * arm-dis.c (print_insn_coprocessor): Added support for quarter
- float bitfield format.
- (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
- quarter float bitfield format.
-
-2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
-
- * configure: Regenerated.
-
-2015-07-03 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
- * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
- PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
-
-2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
- Cesar Philippidis <cesar@codesourcery.com>
-
- * nios2-dis.c (nios2_extract_opcode): New.
- (nios2_disassembler_state): New.
- (nios2_find_opcode_hash): Use mach parameter to select correct
- disassembler state.
- (nios2_print_insn_arg): Extend to support new R2 argument letters
- and formats.
- (print_insn_nios2): Check for 16-bit instruction at end of memory.
- * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
- (NIOS2_NUM_OPCODES): Rename to...
- (NIOS2_NUM_R1_OPCODES): This.
- (nios2_r2_opcodes): New.
- (NIOS2_NUM_R2_OPCODES): New.
- (nios2_num_r2_opcodes): New.
- (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
- (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
- (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
- (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
- (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
-
-2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
-
- * i386-dis.c (OP_Mwaitx): New.
- (rm_table): Add monitorx/mwaitx.
- * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
- and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
- (operand_type_init): Add CpuMWAITX.
- * i386-opc.h (CpuMWAITX): New.
- (i386_cpu_flags): Add cpumwaitx.
- * i386-opc.tbl: Add monitorx and mwaitx.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
-2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
+ * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
+ issues. No functional changes.
- * ppc-opc.c (insert_ls): Test for invalid LS operands.
- (insert_esync): New function.
- (LS, WC): Use insert_ls.
- (ESYNC): Use insert_esync.
+2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
-2015-06-22 Nick Clifton <nickc@redhat.com>
+ * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
+ (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
+ (RTT): Remove duplicate.
+ (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
+ (PCT_CONFIG*): Remove.
+ (D1L, D1H, D2H, D2L): Define.
- * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
- requested region lies beyond it.
- * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
- looking for 32-bit insns.
- * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
- data.
- * sh-dis.c (print_insn_sh): Likewise.
- * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
- blocks of instructions.
- * vax-dis.c (print_insn_vax): Check that the requested address
- does not clash with the stop_vma.
+2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
-2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
+ * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
- * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
- * ppc-opc.c (FXM4): Add non-zero optional value.
- (TBR): Likewise.
- (SXL): Likewise.
- (insert_fxm): Handle new default operand value.
- (extract_fxm): Likewise.
- (insert_tbr): Likewise.
- (extract_tbr): Likewise.
+2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
-2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
+ * arc-tbl.h (invld07): Remove.
+ * arc-ext-tbl.h: New file.
+ * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
+ * arc-opc.c (arc_opcodes): Add ext-tbl include.
- * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
+2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
-2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
+ Fix -Wstack-usage warnings.
+ * aarch64-dis.c (print_operands): Substitute size.
+ * aarch64-opc.c (print_register_offset_address): Substitute tblen.
- * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
+2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
-2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
+ * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
+ to get a proper diagnostic when an invalid ASR register is used.
- * ppc-opc.c: Add comment accidentally removed by old commit.
- (MTMSRD_L): Delete.
+2016-03-22 Nick Clifton <nickc@redhat.com>
-2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
+ * configure: Regenerate.
- * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
-2015-06-04 Nick Clifton <nickc@redhat.com>
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_3bit_dst): New function.
+ (extract_nps_3bit_dst): New function.
+ (insert_nps_3bit_src2): New function.
+ (extract_nps_3bit_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 include.
- PR 18474
- * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
-2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+ * arc-opc.c (arc_flag_classes): Convert all flag classes to use
+ the new class enum values.
- * arm-dis.c (arm_opcodes): Add "setpan".
- (thumb_opcodes): Add "setpan".
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
-2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+ * arc-dis.c (print_insn_arc): Handle nps400.
- * arm-dis.c (select_arm_features): Rework to avoid used of redefined
- macros.
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
-2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+ * arc-opc.c (BASE): Delete.
- * aarch64-tbl.h (aarch64_feature_rdma): New.
- (RDMA): New.
- (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
+2016-03-18 Nick Clifton <nickc@redhat.com>
-2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+ PR target/19721
+ * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
+ of MOV insn that aliases an ORR insn.
- * aarch64-tbl.h (aarch64_feature_lor): New.
- (LOR): New.
- (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
- "stllrb", "stllrh".
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc-2.c: Regenerate.
+2016-03-16 Jiong Wang <jiong.wang@arm.com>
-2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
+ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
- * aarch64-opc.c (F_ARCHEXT): New.
- (aarch64_sys_regs): Add "pan".
- (aarch64_sys_reg_supported_p): New.
- (aarch64_pstatefields): Add "pan".
- (aarch64_pstatefield_supported_p): New.
+2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
-2015-06-01 Jan Beulich <jbeulich@suse.com>
+ * mcore-opc.h: Add const qualifiers.
+ * microblaze-opc.h (struct op_code_struct): Likewise.
+ * sh-opc.h: Likewise.
+ * tic4x-dis.c (tic4x_print_indirect): Likewise.
+ (tic4x_print_op): Likewise.
- * i386-tbl.h: Regenerate.
+2016-03-02 Alan Modra <amodra@gmail.com>
-2015-06-01 Jan Beulich <jbeulich@suse.com>
+ * or1k-desc.h: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * rl78-decode.c: Regenerate.
- * i386-dis.c (print_insn): Swap rounding mode specifier and
- general purpose register in Intel mode.
+2016-03-01 Nick Clifton <nickc@redhat.com>
-2015-06-01 Jan Beulich <jbeulich@suse.com>
+ PR target/19747
+ * rl78-dis.c (print_insn_rl78_common): Fix typo.
- * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
- * i386-tbl.h: Regenerate.
+2016-02-24 Renlin Li <renlin.li@arm.com>
-2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
+ * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
+ (print_insn_coprocessor): Support fp16 instructions.
- * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
- * i386-init.h: Regenerated.
+2016-02-24 Renlin Li <renlin.li@arm.com>
-2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
+ * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
+ vminnm, vrint(mpna).
- PR binutis/18386
- * i386-dis.c: Add comments for '@'.
- (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
- (enum x86_64_isa): New.
- (isa64): Likewise.
- (print_i386_disassembler_options): Add amd64 and intel64.
- (print_insn): Handle amd64 and intel64.
- (putop): Handle '@'.
- (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
- * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
- * i386-opc.h (AMD64): New.
- (CpuIntel64): Likewise.
- (i386_cpu_flags): Add cpuamd64 and cpuintel64.
- * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
- Mark direct call/jmp without Disp16|Disp32 as Intel64.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2016-02-24 Renlin Li <renlin.li@arm.com>
-2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
+ * arm-dis.c (print_insn_coprocessor): Check co-processor number for
+ cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
- * ppc-opc.c (IH) New define.
- (powerpc_opcodes) <wait>: Do not enable for POWER7.
- <tlbie>: Add RS operand for POWER7.
- <slbia>: Add IH operand for POWER6.
+2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
-2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
+ * i386-dis.c (print_insn): Parenthesize expression to prevent
+ truncated addresses.
+ (OP_J): Likewise.
- * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
- direct branch.
- (jmp): Likewise.
- * i386-tbl.h: Regenerated.
+2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
+ Janek van Oirschot <jvanoirs@synopsys.com>
-2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * configure.ac: Support bfd_iamcu_arch.
- * disassemble.c (disassembler): Support bfd_iamcu_arch.
- * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
- CPU_IAMCU_COMPAT_FLAGS.
- (cpu_flags): Add CpuIAMCU.
- * i386-opc.h (CpuIAMCU): New.
- (i386_cpu_flags): Add cpuiamcu.
- * configure: Regenerated.
- * i386-init.h: Likewise.
- * i386-tbl.h: Likewise.
+ * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
+ variable.
-2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
+2016-02-04 Nick Clifton <nickc@redhat.com>
- PR binutis/18386
- * i386-dis.c (X86_64_E8): New.
- (X86_64_E9): Likewise.
- Update comments on 'T', 'U', 'V'. Add comments for '^'.
- (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
- (x86_64_table): Add X86_64_E8 and X86_64_E9.
- (mod_table): Replace {T|} with ^ on Jcall/Jmp.
- (putop): Handle '^'.
- (OP_J): Ignore the operand size prefix in 64-bit. Don't check
- REX_W.
-
-2015-04-30 DJ Delorie <dj@redhat.com>
-
- * disassemble.c (disassembler): Choose suitable disassembler based
- on E_ABI.
- * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
- it to decode mul/div insns.
- * rl78-decode.c: Regenerate.
- * rl78-dis.c (print_insn_rl78): Rename to...
- (print_insn_rl78_common): ...this, take ISA parameter.
- (print_insn_rl78): New.
- (print_insn_rl78_g10): New.
- (print_insn_rl78_g13): New.
- (print_insn_rl78_g14): New.
- (rl78_get_disassembler): New.
-
-2015-04-29 Nick Clifton <nickc@redhat.com>
-
- * po/fr.po: Updated French translation.
-
-2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-opc.c (DCBT_EO): New define.
- (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
- <lharx>: Likewise.
- <stbcx.>: Likewise.
- <sthcx.>: Likewise.
- <waitrsv>: Do not enable for POWER7 and later.
- <waitimpl>: Likewise.
- <dcbt>: Default to the two operand form of the instruction for all
- "old" cpus. For "new" cpus, use the operand ordering that matches
- whether the cpu is server or embedded.
- <dcbtst>: Likewise.
-
-2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
-
- * s390-opc.c: New instruction type VV0UU2.
- * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
- and WFC.
-
-2015-04-23 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
- * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
- vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
- (vfpclasspd, vfpclassps): Add %XZ.
-
-2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (PREFIX_UD_SHIFT): Removed.
- (PREFIX_UD_REPZ): Likewise.
- (PREFIX_UD_REPNZ): Likewise.
- (PREFIX_UD_DATA): Likewise.
- (PREFIX_UD_ADDR): Likewise.
- (PREFIX_UD_LOCK): Likewise.
-
-2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (prefix_requirement): Removed.
- (print_insn): Don't set prefix_requirement. Check
- dp->prefix_requirement instead of prefix_requirement.
-
-2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/17898
- * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
- (PREFIX_MOD_0_0FC7_REG_6): This.
- (PREFIX_MOD_3_0FC7_REG_6): New.
- (PREFIX_MOD_3_0FC7_REG_7): Likewise.
- (prefix_table): Replace PREFIX_0FC7_REG_6 with
- PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
- PREFIX_MOD_3_0FC7_REG_7.
- (mod_table): Replace PREFIX_0FC7_REG_6 with
- PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
- PREFIX_MOD_3_0FC7_REG_7.
-
-2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
- (PREFIX_MANDATORY_REPNZ): Likewise.
- (PREFIX_MANDATORY_DATA): Likewise.
- (PREFIX_MANDATORY_ADDR): Likewise.
- (PREFIX_MANDATORY_LOCK): Likewise.
- (PREFIX_MANDATORY): Likewise.
- (PREFIX_UD_SHIFT): Set to 8
- (PREFIX_UD_REPZ): Updated.
- (PREFIX_UD_REPNZ): Likewise.
- (PREFIX_UD_DATA): Likewise.
- (PREFIX_UD_ADDR): Likewise.
- (PREFIX_UD_LOCK): Likewise.
- (PREFIX_IGNORED_SHIFT): New.
- (PREFIX_IGNORED_REPZ): Likewise.
- (PREFIX_IGNORED_REPNZ): Likewise.
- (PREFIX_IGNORED_DATA): Likewise.
- (PREFIX_IGNORED_ADDR): Likewise.
- (PREFIX_IGNORED_LOCK): Likewise.
- (PREFIX_OPCODE): Likewise.
- (PREFIX_IGNORED): Likewise.
- (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
- (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
- (three_byte_table): Likewise.
- (mod_table): Likewise.
- (mandatory_prefix): Renamed to ...
- (prefix_requirement): This.
- (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
- Update PREFIX_90 entry.
- (get_valid_dis386): Check prefix_requirement to see if a prefix
- should be ignored.
- (print_insn): Replace mandatory_prefix with prefix_requirement.
-
-2015-04-15 Renlin Li <renlin.li@arm.com>
-
- * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
- use it for ssat and ssat16.
- (print_insn_thumb32): Add handle case for 'D' control code.
-
-2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
- H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
- * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
- PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
- PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
- PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
- (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
- Fill prefix_requirement field.
- (struct dis386): Add prefix_requirement field.
- (dis386): Fill prefix_requirement field.
- (dis386_twobyte): Ditto.
- (twobyte_has_mandatory_prefix_: Remove.
- (reg_table): Fill prefix_requirement field.
- (prefix_table): Ditto.
- (x86_64_table): Ditto.
- (three_byte_table): Ditto.
- (xop_table): Ditto.
- (vex_table): Ditto.
- (vex_len_table): Ditto.
- (vex_w_table): Ditto.
- (mod_table): Ditto.
- (bad_opcode): Ditto.
- (print_insn): Use prefix_requirement.
- (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
- FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
- (float_reg): Ditto.
-
-2015-03-30 Mike Frysinger <vapier@gentoo.org>
-
- * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
-
-2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
-
- * Makefile.in: Regenerated.
-
-2015-03-25 Anton Blanchard <anton@samba.org>
-
- * ppc-dis.c (disassemble_init_powerpc): Only initialise
- powerpc_opcd_indices and vle_opcd_indices once.
-
-2015-03-25 Anton Blanchard <anton@samba.org>
-
- * ppc-opc.c (powerpc_opcodes): Add slbfee.
-
-2015-03-24 Terry Guo <terry.guo@arm.com>
-
- * arm-dis.c (opcode32): Updated to use new arm feature struct.
- (opcode16): Likewise.
- (coprocessor_opcodes): Replace bit with feature struct.
- (neon_opcodes): Likewise.
- (arm_opcodes): Likewise.
- (thumb_opcodes): Likewise.
- (thumb32_opcodes): Likewise.
- (print_insn_coprocessor): Likewise.
- (print_insn_arm): Likewise.
- (select_arm_features): Follow new feature struct.
+ PR target/19561
+ * msp430-dis.c (print_insn_msp430): Add a special case for
+ decoding an RRC instruction with the ZC bit set in the extension
+ word.
-2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
- * i386-dis.c (rm_table): Add clzero.
- * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
- Add CPU_CLZERO_FLAGS.
- (cpu_flags): Add CpuCLZERO.
- * i386-opc.h: Add CpuCLZERO.
- * i386-opc.tbl: Add clzero.
- * i386-init.h: Re-generated.
- * i386-tbl.h: Re-generated.
+ * cgen-ibld.in (insert_normal): Rework calculation of shift.
+ * epiphany-ibld.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
-2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
- * mips-opc.c (decode_mips_operand): Fix constraint issues
- with u and y operands.
+ * epiphany-dis.c: Regenerated from latest cpu files.
-2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
+2016-02-01 Michael McConville <mmcco@mykolab.com>
- * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
+ * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
+ test bit.
-2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+2016-01-25 Renlin Li <renlin.li@arm.com>
- * s390-opc.c: Add new IBM z13 instructions.
- * s390-opc.txt: Likewise.
+ * arm-dis.c (mapping_symbol_for_insn): New function.
+ (find_ifthen_state): Call mapping_symbol_for_insn().
-2015-03-10 Renlin Li <renlin.li@arm.com>
+2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
- * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
- stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
- related alias.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis-2.c: Likewise.
- * aarch64-opc-2.c: Likewise.
+ * aarch64-opc.c (operand_general_constraint_met_p): Check validity
+ of MSR UAO immediate operand.
-2015-03-03 Jiong Wang <jiong.wang@arm.com>
+2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
- * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
+ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
+ instruction support.
-2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
+2016-01-17 Alan Modra <amodra@gmail.com>
- * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
- arch_sh_up.
- (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
- arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
+ * configure: Regenerate.
-2015-02-23 Vinay <Vinay.G@kpit.com>
+2016-01-14 Nick Clifton <nickc@redhat.com>
- * rl78-decode.opc (MOV): Added space between two operands for
- 'mov' instruction in index addressing mode.
+ * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
+ instructions that can support stack pointer operations.
* rl78-decode.c: Regenerate.
+ * rl78-dis.c: Fix display of stack pointer in MOVW based
+ instructions.
-2015-02-19 Pedro Alves <palves@redhat.com>
-
- * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
-
-2015-02-10 Pedro Alves <palves@redhat.com>
- Tom Tromey <tromey@redhat.com>
+2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
- * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
- microblaze_and, microblaze_xor.
- * microblaze-opc.h (opcodes): Adjust.
+ * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
+ testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
+ erxtatus_el1 and erxaddr_el1.
-2015-01-28 James Bowman <james.bowman@ftdichip.com>
+2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
- * Makefile.am: Add FT32 files.
- * configure.ac: Handle FT32.
- * disassemble.c (disassembler): Call print_insn_ft32.
- * ft32-dis.c: New file.
- * ft32-opc.c: New file.
- * Makefile.in: Regenerate.
- * configure: Regenerate.
- * po/POTFILES.in: Regenerate.
+ * arm-dis.c (arm_opcodes): Add "esb".
+ (thumb_opcodes): Likewise.
-2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
- * nds32-asm.c (keyword_sr): Add new system registers.
+ * ppc-opc.c <xscmpnedp>: Delete.
+ <xvcmpnedp>: Likewise.
+ <xvcmpnedp.>: Likewise.
+ <xvcmpnesp>: Likewise.
+ <xvcmpnesp.>: Likewise.
-2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
- * s390-dis.c (s390_extract_operand): Support vector register
- operands.
- (s390_print_insn_with_opcode): Support new operands types and add
- new handling of optional operands.
- * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
- and include opcode/s390.h instead.
- (struct op_struct): New field `flags'.
- (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
- (dumpTable): Dump flags.
- (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
- string.
- * s390-opc.c: Add new operands types, instruction formats, and
- instruction masks.
- (s390_opformats): Add new formats for .insn.
- * s390-opc.txt: Add new instructions.
+ PR gas/13050
+ * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
+ addition to ISA_A.
-201
5-01-01 Alan Modra <amodra@gmail.com>
+201
6-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2014
+For older changes see ChangeLog-2015
\f
-Copyright (C) 2015 Free Software Foundation, Inc.
+Copyright (C) 2016 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff