+2006-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
+ (twobyte_uses_DATA_prefix): This.
+ (twobyte_uses_REPNZ_prefix): New.
+ (twobyte_uses_REPZ_prefix): Likewise.
+ (threebyte_0x38_uses_DATA_prefix): Likewise.
+ (threebyte_0x38_uses_REPNZ_prefix): Likewise.
+ (threebyte_0x38_uses_REPZ_prefix): Likewise.
+ (threebyte_0x3a_uses_DATA_prefix): Likewise.
+ (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
+ (threebyte_0x3a_uses_REPZ_prefix): Likewise.
+ (print_insn): Updated checking usages of DATA/REPNZ/REPZ
+ prefixes.
+
+2006-11-06 Troy Rollo <troy@corvu.com.au>
+
+ * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
+
+2006-11-01 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-opc.h (score_opcodes): Delete modifier '0x'.
+
+2006-10-30 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
+ (get_sym_code_type): New function.
+ (print_insn): Search for mapping symbols.
+
+2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-dis.c (print_insn): Correct the error code to print
+ correct PCE instruction disassembly.
+
+2006-10-26 Ben Elliston <bje@au.ibm.com>
+ Anton Blanchard <anton@samba.org>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
+ AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
+ (POWER6): Define.
+ (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
+ "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
+ Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
+ "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
+ "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
+ "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
+ "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
+ "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
+ "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
+ "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
+ "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
+ "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
+ "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
+ "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
+ "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
+ "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
+ "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
+ "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
+ "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
+ "diexq" and "diexq." opcodes.
+
+2006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
+
+2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
+ Yukishige Shibata <shibata@rd.scei.sony.co.jp>
+ Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
+ Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * spu-dis.c: New file.
+ * spu-opc.c: New file.
+ * configure.in: Add SPU support.
+ * disassemble.c: Likewise.
+ * Makefile.am: Likewise. Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
+
+ * ppc-opc.c (CELL): New define.
+ (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
+ cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
+ VMX instructions.
+ * ppc-dis.c (powerpc_dialect): Handle cell.
+
+2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
+ * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
+ amdfam10 architecture.
+ (PREGRP37): NEW.
+ (print_insn): Disallow REP prefix for POPCNT.
+
+2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
+
+ * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
+ duplicating it.
+
+2006-10-18 Dave Brolley <brolley@redhat.com>
+
+ * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
+ * configure: Regenerated.
+
+2006-09-29 Alan Modra <amodra@bigpond.net.au>
+
+ * po/POTFILES.in: Regenerate.
+
+2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Ian Lance Taylor <ian@wasabisystems.com>
+ Ben Elliston <bje@wasabisystems.com>
+
+ * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
+ only be used with the default multiply-add operation, so if N is
+ set, don't bother printing X. Add new iwmmxt instructions.
+ (IWMMXT_INSN_COUNT): Update.
+ (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
+ with a 'c' suffix.
+ (print_insn_coprocessor): Check for iWMMXt2. Handle format
+ specifiers 'r', 'i'.
+
+2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
+ PR binutils/3100
+ * i386-dis.c (prefix_user_table): Fix the second operand of
+ maskmovdqu instruction to allow only %xmm register instead of
+ both %xmm register and memory.
+
+2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/3235
+ * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
+ address size prefix.
+
+2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-dis.c: New file.
+ * score-opc.h: New file.
+ * Makefile.am: Add Score files.
+ * Makefile.in: Regenerate.
+ * configure.in: Add support for Score target.
+ * configure: Regenerate.
+ * disassemble.c: Add support for Score target.
+
+2006-09-16 Nick Clifton <nickc@redhat.com>
+ Pedro Alves <pedro_alves@portugalmail.pt>
+
+ * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
+ macros defined in bfd.h.
+ * cris-dis.c: Likewise.
+ * h8300-dis.c: Likewise.
+ * i386-dis.c: Likewise.
+ * ia64-gen.c: Likewise.
+ * mips-dis: Likewise.
+
+2006-09-04 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
+
+2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (three_byte_table): Expand to 256 elements.
+
+2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
+ PR binutils/3000
+ * i386-dis.c (MXC,EMC): Define.
+ (OP_MXC): New function to handle cvt* (convert instructions) between
+ %xmm and %mm register correctly.
+ (OP_EMC): ditto.
+ (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
+ instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
+ with EMC/MXC.
+
+2006-07-29 Richard Sandiford <richard@codesourcery.com>
+
+ * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
+ "fdaddl" entry.
+
+2006-07-19 Paul Brook <paul@codesourcery.com>
+
+ * armd-dis.c (arm_opcodes): Fix rbit opcode.
+
+2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
+ "sldt", "str" and "smsw".
+
+2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/2829
+ * i386-dis.c (GRP11_C6): NEW.
+ (GRP11_C7): Likewise.
+ (GRP12): Updated.
+ (GRP13): Likewise.
+ (GRP14): Likewise.
+ (GRP15): Likewise.
+ (GRP16): Likewise.
+ (GRPAMD): Likewise.
+ (GRPPADLCK1): Likewise.
+ (GRPPADLCK2): Likewise.
+ (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
+ respectively.
+ (grps): Add entries for GRP11_C6 and GRP11_C7.
+
+2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Michael Meissner <michael.meissner@amd.com>
+
+ * i386-dis.c (dis386): Add support for 4 operand instructions. Add
+ support for amdfam10 SSE4a/ABM instructions. Modify all
+ initializer macros to have additional arguments. Disallow REP
+ prefix for non-string instructions.
+ (print_insn): Ditto.
+
+2006-07-05 Julian Brown <julian@codesourcery.com>
+
+ * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
+
+2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
+ (twobyte_has_modrm): Set 1 for 0x1f.
+
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (NOP_Fixup): Removed.
projects / deliverable / binutils-gdb.git / blobdiff