[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 221f8f7802855d3717b14e164debcfe1c010de91..6782a7ebea2f51fe70d8c2b650df5b3f2152653d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,118 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-tbl.h (QL_V3SAMEH): New.
+       (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
+       fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
+       fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
+       fcmgt, facgt and fminp to the vector three same group.
+
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_simd_f16): New.
+       (SIMD_F16): New.
+
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
+       removed statement.
+       (aarch64_pstatefield_supported_p): Move feature checks for AT
+       registers ..
+       (aarch64_sys_ins_reg_supported_p): .. to here.
+
+2015-12-12  Alan Modra  <amodra@gmail.com>
+
+       PR 19359
+       * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
+       (powerpc_opcodes): Remove single-operand mfcr.
+
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm.c (aarch64_ins_hint): New.
+       * aarch64-asm.h (aarch64_ins_hint): Declare.
+       * aarch64-dis.c (aarch64_ext_hint): New.
+       * aarch64-dis.h (aarch64_ext_hint): Declare.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-opc.c (aarch64_hint_options): New.
+       * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
+
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
+
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
+       pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
+       pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
+       pmscr_el2.
+       (aarch64_sys_reg_supported_p): Add architecture feature tests for
+       the new registers.
+
+2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
+       (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
+       feature test for "s1e1rp" and "s1e1wp".
+
+2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
+       (aarch64_sys_ins_reg_supported_p): New.
+
+2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
+       with aarch64_sys_ins_reg_has_xt.
+       (aarch64_ext_sysins_op): Likewise.
+       * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
+       (F_HASXT): New.
+       (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
+       (aarch64_sys_regs_dc): Likewise.
+       (aarch64_sys_regs_at): Likewise.
+       (aarch64_sys_regs_tlbi): Likewise.
+       (aarch64_sys_ins_reg_has_xt): New.
+
+2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "uao".
+       (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
+       (aarch64_pstatefields): Add "uao".
+       (aarch64_pstatefield_supported_p): Add checks for "uao".
+
+2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
+       "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
+       "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
+       (aarch64_sys_reg_supported_p): Add architecture feature tests for
+       new registers.
+
+2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-tbl.h (aarch64_feature_ras): New.
+       (RAS): New.
+       (aarch64_opcode_table): Add "esb".
+
+2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (MOD_0F01_REG_5): New.
+       (RM_0F01_REG_5): Likewise.
+       (reg_table): Use MOD_0F01_REG_5.
+       (mod_table): Add MOD_0F01_REG_5.
+       (rm_table): Add RM_0F01_REG_5.
+       * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
+       (cpu_flags): Add CpuOSPKE.
+       * i386-opc.h (CpuOSPKE): New.
+       (i386_cpu_flags): Add cpuospke.
+       * i386-opc.tbl: Add rdpkru and wrpkru instructions.
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
 2015-12-07  DJ Delorie  <dj@redhat.com>
 
        * rl78-decode.opc: Enable MULU for all ISAs.