[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
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+++ b/opcodes/ChangeLog
@@ -1,3 +1,56 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-tbl.h (QL_V3SAMEH): New.
+       (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
+       fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
+       fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
+       fcmgt, facgt and fminp to the vector three same group.
+
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_simd_f16): New.
+       (SIMD_F16): New.
+
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
+       removed statement.
+       (aarch64_pstatefield_supported_p): Move feature checks for AT
+       registers ..
+       (aarch64_sys_ins_reg_supported_p): .. to here.
+
+2015-12-12  Alan Modra  <amodra@gmail.com>
+
+       PR 19359
+       * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
+       (powerpc_opcodes): Remove single-operand mfcr.
+
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm.c (aarch64_ins_hint): New.
+       * aarch64-asm.h (aarch64_ins_hint): Declare.
+       * aarch64-dis.c (aarch64_ext_hint): New.
+       * aarch64-dis.h (aarch64_ext_hint): Declare.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-opc.c (aarch64_hint_options): New.
+       * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
+
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
+
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
+       pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
+       pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
+       pmscr_el2.
+       (aarch64_sys_reg_supported_p): Add architecture feature tests for
+       the new registers.
+
 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".