+2014-10-31 Andrew Pinski <apinski@cavium.com>
+ Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
+
+ * mips-dis.c (mips_arch_choices): Add octeon3.
+ * mips-opc.c (IOCT): Include INSN_OCTEON3.
+ (IOCT2): Likewise.
+ (IOCT3): New define.
+ (IVIRT): New define.
+ (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+ tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
+ IVIRT instructions.
+ Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
+ operand for IOCT3.
+
+2014-10-29 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+
+2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
+ (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
+ MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
+ size and format initializers. Merge 'b' arguments into 'j'.
+ (NIOS2_NUM_OPCODES): Adjust definition.
+ (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
+ (nios2_opcodes): Adjust.
+ (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
+ * nios2-dis.c (INSNLEN): Update comment.
+ (nios2_hash_init, nios2_hash): Delete.
+ (OPCODE_HASH_SIZE): New.
+ (nios2_r1_extract_opcode): New.
+ (nios2_disassembler_state): New.
+ (nios2_r1_disassembler_state): New.
+ (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
+ (nios2_find_opcode_hash): Use state object.
+ (bad_opcode): New.
+ (nios2_print_insn_arg): Add op parameter. Use it to access
+ format. Remove 'b' case.
+ (nios2_disassemble): Remove special case for nop. Remove
+ hard-coded instruction size.
+
+2014-10-21 Jan Beulich <jbeulich@suse.com>
+
+ * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
+
+2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
+ entries.
+ Annotate several instructions with the HWCAP2_VIS3B hwcap.
+
+2014-10-15 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
+ `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
+ Annotate table with HWCAP2 bits.
+ Add instructions xmontmul, xmontsqr, xmpmul.
+ (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
+ r,i,%mwait' and `rd %mwait,r' instructions.
+ Add rd/wr instructions for accessing the %mcdper ancillary state
+ register.
+ (sparc-opcodes): Add sparc5/vis4.0 instructions:
+ subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
+ fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
+ fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
+ fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
+ fpsubus16, and faligndatai.
+ * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
+ ancillary state register to the table.
+ (print_insn_sparc): Handle the %mcdper ancillary state register.
+ (print_insn_sparc): Handle new operand type '}'.
+
+2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (MOD_0F20): Removed.
+ (MOD_0F21): Likewise.
+ (MOD_0F22): Likewise.
+ (MOD_0F23): Likewise.
+ (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
+ MOD_0F23 with "movZ".
+ (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
+ (OP_R): Check mod/rm byte and call OP_E_register.
+
+2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
+ keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
+ keyword_aridxi): Add audio ISA extension.
+ (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
+ keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
+ keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
+ for nds32-dis.c using.
+ (build_opcode_syntax): Remove dead code.
+ (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
+ parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
+ parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
+ operand parser.
+ * nds32-asm.h: Declare.
+ * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
+ decoding by switch.
+
2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>
projects / deliverable / binutils-gdb.git / blobdiff