* rl78-decode.opc (rl78_decode_opcode): Fix typo.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c593d9dbd40ed255915b05c339e5552aff386112..7208b2814d8fdabd181523ebf067d4b56d96b8cd 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,9 +1,103 @@
+2013-02-27  Alan Modra  <amodra@gmail.com>
+
+       * rl78-decode.opc (rl78_decode_opcode): Fix typo.
+       * rl78-decode.c: Regenerate.
+
+2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
+
+       * rl78-decode.opc: Fix encoding of DIVWU insn.
+       * rl78-decode.c: Regenerate.
+
+2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/15159
+       * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
+
+       * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
+       (cpu_flags): Add CpuSMAP.
+
+       * i386-opc.h (CpuSMAP): New.
+       (i386_cpu_flags): Add cpusmap.
+
+       * i386-opc.tbl: Add clac and stac.
+
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
+2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
+
+       * metag-dis.c: Initialize outf->bytes_per_chunk to 4
+       which also makes the disassembler output be in little
+       endian like it should be.
+
+2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
+       fields to NULL.
+       (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
+
+2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips-dis.c (is_compressed_mode_p): Only match symbols from the
+       section disassembled.
+
+2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * arm-dis.c: Update strht pattern.
+
+2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
+
+       * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
+       single-float.  Disable ll, lld, sc and scd for EE.  Disable the
+       trunc.w.s macro for EE.
+
+2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
+            Andrew Jenner <andrew@codesourcery.com>
+
+       Based on patches from Altera Corporation.
+
+       * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
+       nios2-opc.c.
+       * Makefile.in: Regenerated.
+       * configure.in: Add case for bfd_nios2_arch.
+       * configure: Regenerated.
+       * disassemble.c (ARCH_nios2): Define.
+       (disassembler): Add case for bfd_arch_nios2.
+       * nios2-dis.c: New file.
+       * nios2-opc.c: New file.
+
+2013-02-04  Alan Modra  <amodra@gmail.com>
+
+       * po/POTFILES.in: Regenerate.
+       * rl78-decode.c: Regenerate.
+       * rx-decode.c: Regenerate.
+
+2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
+       ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
+       * aarch64-asm.c (convert_xtl_to_shll): New function.
+       (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
+       calling convert_xtl_to_shll.
+       * aarch64-dis.c (convert_shll_to_xtl): New function.
+       (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
+       calling convert_shll_to_xtl.
+       * aarch64-gen.c: Update copyright year.
+       * aarch64-asm-2.c: Re-generate.
+       * aarch64-dis-2.c: Re-generate.
+       * aarch64-opc-2.c: Re-generate.
+
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+       * v850-dis.c: Add support for e3v5 architecture.
+       * v850-opc.c: Likewise.
+
 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
        * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
        * aarch64-opc.c (operand_general_constraint_met_p): For
-       AARCH64_MOD_LSL, move the range check on the shift amount before the 
+       AARCH64_MOD_LSL, move the range check on the shift amount before the
        alignment check; change to call set_sft_amount_out_of_range_error
        instead of set_imm_out_of_range_error.
        * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.