+2019-10-07 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
+ (cmpsd): Likewise. Move EsSeg to other operand.
+ * opcodes/i386-tbl.h: Re-generate.
+
+2019-09-23 Alan Modra <amodra@gmail.com>
+
+ * m68k-dis.c: Include cpu-m68k.h
+
+2019-09-23 Alan Modra <amodra@gmail.com>
+
+ * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
+ "elf/mips.h" earlier.
+
+2018-09-20 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/25012
+ * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
+ with SReg operand.
+ * i386-tbl.h: Re-generate.
+
+2019-09-18 Alan Modra <amodra@gmail.com>
+
+ * arc-ext.c: Update throughout for bfd section macro changes.
+
+2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
+
+ * Makefile.in: Re-generate.
+ * configure: Re-generate.
+
+2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
+
+ * riscv-opc.c (riscv_opcodes): Change subset field
+ to insn_class field for all instructions.
+ (riscv_insn_types): Likewise.
+
+2019-09-16 Phil Blundell <pb@pbcl.net>
+
+ * configure: Regenerated.
+
+2019-09-10 Miod Vallat <miod@online.fr>
+
+ PR 24982
+ * m68k-opc.c: Correct aliases for tdivsl and tdivul.
+
+2019-09-09 Phil Blundell <pb@pbcl.net>
+
+ binutils 2.33 branch created.
+
+2019-09-03 Nick Clifton <nickc@redhat.com>
+
+ PR 24961
+ * tic30-dis.c (get_indirect_operand): Check for bufcnt being
+ greater than zero before indexing via (bufcnt -1).
+
+2019-09-03 Nick Clifton <nickc@redhat.com>
+
+ PR 24958
+ * mmix-dis.c (MAX_REG_NAME_LEN): Define.
+ (MAX_SPEC_REG_NAME_LEN): Define.
+ (struct mmix_dis_info): Use defined constants for array lengths.
+ (get_reg_name): New function.
+ (get_sprec_reg_name): New function.
+ (print_insn_mmix): Use new functions.
+
+2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
+ (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
+ (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
+
+2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
+ tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
+ (aarch64_sys_reg_supported_p): Update checks for the above.
+
+2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
+ cases MVE_SQRSHRL and MVE_UQRSHLL.
+ (print_insn_mve): Add case for specifier 'k' to check
+ specific bit of the instruction.
+
+2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
+
+ PR 24854
+ * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
+ encountering an unknown machine type.
+ (print_insn_arc): Handle arc_insn_length returning 0. In error
+ cases return -1 rather than calling abort.
+
+2019-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
+ (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
+ IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
+
+ * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
+ instructions.
+
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
+ fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
+
+ * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
+ fscsr.
+
+2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
+ and MPY class instructions.
+ (parse_option): Add nps400 option.
+ (print_arc_disassembler_options): Add nps400 info.
+
+2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext-tbl.h (bspeek): Remove it, added to main table.
+ (bspop): Likewise.
+ (modapp): Likewise.
+ * arc-opc.c (RAD_CHK): Add.
+ * arc-tbl.h: Regenerate.
+
2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.