[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 36c5af2739975842d5527c1ddc2634e71d513f3e..776aa0fee2433559050b1c2cc01388112539be5d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,118 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): New entries for
+       scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
+       (aarch64_sys_reg_supported_p): New checks for above.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
+       (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
+       with the hint immediate.
+       * aarch64-opc.c (aarch64_hint_options): New entries for
+       c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
+       (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
+       while checking for HINT_OPD_F_NOPRINT flag.
+       * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
+       extract value.
+       * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
+       (aarch64_opcode_table): Add entry for BTI.
+       (AARCH64_OPERANDS): Add new description for BTI targets.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): New entries for
+       rndr and rndrrs.
+       (aarch64_sys_reg_supported_p): New check for above.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
+       (aarch64_sys_ins_reg_supported_p): New check for above.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
+       AARCH64_OPND_SYSREG_SR.
+       * aarch64-opc.c (aarch64_print_operand): Likewise.
+       (aarch64_sys_regs_sr): Define table.
+       (aarch64_sys_ins_reg_supported_p): Check for RCTX with
+       AARCH64_FEATURE_PREDRES.
+       * aarch64-tbl.h (aarch64_feature_predres): New.
+       (PREDRES, PREDRES_INSN): New.
+       (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
+       (AARCH64_OPERANDS): Add new description for SYSREG_SR.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_sb): New.
+       (SB, SB_INSN): New.
+       (aarch64_opcode_table): Add entry for sb.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_flagmanip): New.
+       (aarch64_feature_frintts): New.
+       (FLAGMANIP, FRINTTS): New.
+       (aarch64_opcode_table): Add entries for xaflag, axflag
+       and frint[32,64][x,z] instructions.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
+       (ARMV8_5, V8_5_INSN): New.
+
+2018-10-08  Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
+
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (rm_table): Add enclv.
+       * i386-opc.tbl: Add enclv.
+       * i386-tbl.h: Regenerated.
+
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
+       * arm-dis.c (arm_opcodes): Add sb.
+       (thumb32_opcodes): Likewise.
+
+2018-10-05  Richard Henderson  <rth@twiddle.net>
+           Stafford Horne  <shorne@gmail.com>
+
+       * or1k-desc.c: Regenerate.
+       * or1k-desc.h: Regenerate.
+       * or1k-opc.c: Regenerate.
+       * or1k-opc.h: Regenerate.
+       * or1k-opinst.c: Regenerate.
+
+2018-10-05  Richard Henderson  <rth@twiddle.net>
+
+       * or1k-asm.c: Regenerated.
+       * or1k-desc.c: Regenerated.
+       * or1k-desc.h: Regenerated.
+       * or1k-dis.c: Regenerated.
+       * or1k-ibld.c: Regenerated.
+       * or1k-opc.c: Regenerated.
+       * or1k-opc.h: Regenerated.
+       * or1k-opinst.c: Regenerated.
+
+2018-10-05  Richard Henderson  <rth@twiddle.net>
+
+       * or1k-asm.c: Regenerate.
+
 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 
        * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.