-2014-02-21 Ilya Tocar <ilya.tocar@intel.com>
+2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
+ Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+ Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+ Soundararajan <Sounderarajan.D@atmel.com>
+
+ * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
+ (print_insn_avr): Do not select opcode if insn ISA is avrtiny and machine
+ is not avrtiny.
+
+2014-06-26 Philippe De Muyter <phdm@macqel.be>
+
+ * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
+ constants.
+
+2014-06-12 Alan Modra <amodra@gmail.com>
+
+ * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
+ * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
+
+2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (fwait_prefix): New.
+ (ckprefix): Set fwait_prefix.
+ (print_insn): Properly print prefixes before fwait.
+
+2014-06-07 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
+
+2014-06-05 Joel Brobecker <brobecker@adacore.com>
+
+ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
+ bfd's development.sh.
+ * Makefile.in, configure: Regenerate.
+
+2014-06-03 Nick Clifton <nickc@redhat.com>
+
+ * msp430-dis.c (msp430_doubleoperand): Use extension_word to
+ decide when extended addressing is being used.
+
+2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
+
+ * sparc-opc.c (cas): Disable for LEON.
+ (casl): Likewise.
+
+2014-05-20 Alan Modra <amodra@gmail.com>
+
+ * m68k-dis.c: Don't include setjmp.h.
+
+2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (ADDR16_PREFIX): Removed.
+ (ADDR32_PREFIX): Likewise.
+ (DATA16_PREFIX): Likewise.
+ (DATA32_PREFIX): Likewise.
+ (prefix_name): Updated.
+ (print_insn): Simplify data and address size prefixes processing.
+
+2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+
+ * or1k-desc.c: Regenerated.
+ * or1k-desc.h: Likewise.
+ * or1k-opc.c: Likewise.
+ * or1k-opc.h: Likewise.
+ * or1k-opinst.c: Likewise.
+
+2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
+ (I34): New define.
+ (I36): New define.
+ (I66): New define.
+ (I68): New define.
+ * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
+ mips64r5.
+ (parse_mips_dis_option): Update MSA and virtualization support to
+ allow mips64r3 and mips64r5.
+
+2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-opc.c (G3): Remove I4.
+
+2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/16893
+ * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
+ (end_codep): Likewise.
+ (mandatory_prefix): Likewise.
+ (active_seg_prefix): Likewise.
+ (ckprefix): Set active_seg_prefix to the active segment register
+ prefix.
+ (seg_prefix): Removed.
+ (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
+ for prefix index. Ignore the index if it is invalid and the
+ mandatory prefix isn't required.
+ (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
+ mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
+ in used_prefixes here. Don't print unused prefixes. Check
+ active_seg_prefix for the active segment register prefix.
+ Restore the DFLAG bit in sizeflag if the data size prefix is
+ unused. Check the unused mandatory PREFIX_XXX prefixes
+ (append_seg): Only print the segment register which gets used.
+ (OP_E_memory): Check active_seg_prefix for the segment register
+ prefix.
+ (OP_OFF): Likewise.
+ (OP_OFF64): Likewise.
+ (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
+
+2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/16886
+ * config.in: Regenerated.
+ * configure: Likewise.
+ * configure.in: Check if sigsetjmp is available.
+ * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+ (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+ (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
+ * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+ (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+ (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
+ * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+ (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+ (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
+ * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
+ (OPCODES_SIGSETJMP): Likewise.
+ (OPCODES_SIGLONGJMP): Likewise.
+ * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+ (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+ (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
+ * xtensa-dis.c (dis_private): Replace jmp_buf with
+ OPCODES_SIGJMP_BUF.
+ (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+ (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
+ * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
+ (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
+ (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
+
+2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/16891
+ * i386-dis.c (print_insn): Handle prefixes before fwait.
+
+2014-04-26 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
+2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
+ to allow the MIPS XPA ASE.
+ (parse_mips_dis_option): Process the -Mxpa option.
+ * mips-opc.c (XPA): New define.
+ (mips_builtin_opcodes): Add MIPS XPA instructions and move the
+ locations of the ctc0 and cfc0 instructions.
+
+2014-04-22 Christian Svensson <blue@cmd.nu>
+
+ * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
+ * configure.in: Likewise.
+ * disassemble.c: Likewise.
+ * or1k-asm.c: New file.
+ * or1k-desc.c: New file.
+ * or1k-desc.h: New file.
+ * or1k-dis.c: New file.
+ * or1k-ibld.c: New file.
+ * or1k-opc.c: New file.
+ * or1k-opc.h: New file.
+ * or1k-opinst.c: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * openrisc-asm.c: Delete.
+ * openrisc-desc.c: Delete.
+ * openrisc-desc.h: Delete.
+ * openrisc-dis.c: Delete.
+ * openrisc-ibld.c: Delete.
+ * openrisc-opc.c: Delete.
+ * openrisc-opc.h: Delete.
+ * or32-dis.c: Delete.
+ * or32-opc.c: Delete.
+
+2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
+
+ * i386-dis.c (rm_table): Add encls, enclu.
+ * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
+ (cpu_flags): Add CpuSE1.
+ * i386-opc.h (enum): Add CpuSE1.
+ (i386_cpu_flags): Add cpuse1.
+ * i386-opc.tbl: Add encls, enclu.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2014-04-02 Anthony Green <green@moxielogic.com>
+
+ * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
+ instructions, sex.b and sex.s.
+
+2014-03-26 Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
+ instructions.
+
+2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
+
+ * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
+ vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
+ vscatterqps.
+ * i386-tbl.h: Regenerate.
+
+2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
+ %hstick_enable added.
+
+2014-03-19 Nick Clifton <nickc@redhat.com>
+
+ * rx-decode.opc (bwl): Allow for bogus instructions with a size
+ field of 3.
+ (sbwl, ubwl, SCALE): Likewise.
+ * rx-decode.c: Regenerate.
+
+2014-03-12 Alan Modra <amodra@gmail.com>
+
+ * Makefile.in: Regenerate.
+
+2014-03-05 Alan Modra <amodra@gmail.com>
+
+ Update copyright years.
+
+2014-03-04 Heiher <r@hev.cc>
+
+ * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
+
+2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
+ so that they come after the Loongson extensions.
+
+2014-03-03 Alan Modra <amodra@gmail.com>
+
+ * i386-gen.c (process_copyright): Emit copyright notice on one line.
+
+2014-02-28 Alan Modra <amodra@gmail.com>
+
+ * msp430-decode.c: Regenerate.
+
+2014-02-27 Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
+ FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
+
+2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64-opc.c (print_register_offset_address): Call
+ get_int_reg_name to prepare the register name.
+
+2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
+
+ * i386-opc.tbl: Remove wrong variant of vcvtps2ph
+ * i386-tbl.h: Regenerate.
+
+2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
(cpu_flags): Add CpuPREFETCHWT1.
projects / deliverable / binutils-gdb.git / blobdiff