+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_82): Renamed to ...
+ (REG_83): This.
+ (dis386): Updated.
+ (reg_table): Likewise.
+
+2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
+ CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_4VNNIW.
+ * i386-opc.h (enum): (AVX512_4VNNIW): New.
+ (i386_cpu_flags): Add cpuavx512_4vnniw.
+ * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
+ PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
+ CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_4FMAPS.
+ (opcode_modifiers): Add ImplicitQuadGroup modifier.
+ * i386-opc.h (AVX512_4FMAP): New.
+ (i386_cpu_flags): Add cpuavx512_4fmaps.
+ (ImplicitQuadGroup): New.
+ (i386_opcode_modifier): Add implicitquadgroup.
+ * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ Add support for RISC-V architecture.
+ * configure.ac: Add entry for bfd_riscv_arch.
+ * configure: Regenerate.
+ * disassemble.c (disassembler): Add support for riscv.
+ (disassembler_usage): Likewise.
+ * riscv-dis.c: New file.
+ * riscv-opc.c: New file.
+
+2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
+ (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
+ (rm_table): Update the RM_0FAE_REG_7 entry.
+ * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
+ (cpu_flags): Remove CpuPCOMMIT.
+ * i386-opc.h (CpuPCOMMIT): Removed.
+ (i386_cpu_flags): Remove cpupcommit.
+ * i386-opc.tbl: Remove pcommit.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20705
+ * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
+ the highest bit in VEX.vvvv for the 3-byte VEX prefix in
+ 32-bit mode. Don't check vex.register_specifier in 32-bit
+ mode.
+ (OP_VEX): Check for invalid mask registers.
+
+2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20699
+ * i386-dis.c (OP_E_memory): Check addr32flag in stead of
+ sizeflag.
+
+2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20704
+ * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
+
+2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
+ local variable to `index_regno'.
+
+2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-tbl.h: Removed any "inv.+" instructions from the table.
+
+2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
+ usage on ISA basis.
+
+2016-10-11 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20666
+ * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
+
+2016-10-07 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20667
+ * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
+ available.
+
+2016-10-07 Alan Modra <amodra@gmail.com>
+
+ * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * aarch64-opc.c: Spell fall through comments consistently.
+ * i386-dis.c: Likewise.
+ * aarch64-dis.c: Add missing fall through comments.
+ * aarch64-opc.c: Likewise.
+ * arc-dis.c: Likewise.
+ * arm-dis.c: Likewise.
+ * i386-dis.c: Likewise.
+ * m68k-dis.c: Likewise.
+ * mep-asm.c: Likewise.
+ * ns32k-dis.c: Likewise.
+ * sh-dis.c: Likewise.
+ * tic4x-dis.c: Likewise.
+ * tic6x-dis.c: Likewise.
+ * vax-dis.c: Likewise.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * arc-ext.c (create_map): Add missing break.
+ * msp430-decode.opc (encode_as): Likewise.
+ * msp430-decode.c: Regenerate.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
+ * crx-dis.c (print_insn_crx): Likewise.
+
+2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20657
+ * i386-dis.c (putop): Don't assign alt twice.
+
+2016-09-29 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20553
+ * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
+
+2016-09-29 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (L): Make compulsory.
+ (LOPT): New, optional form of L.
+ (HTM_R): Define as LOPT.
+ (L0, L1): Delete.
+ (L32OPT): New, optional for 32-bit L.
+ (L2OPT): New, 2-bit L for dcbf.
+ (SVC_LEC): Update.
+ (L2): Define.
+ (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
+ (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
+ <dcbf>: Use L2OPT.
+ <tlbiel, tlbie>: Use LOPT.
+ <wclr, wclrall>: Use L2.
+
+2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
+
+ * Makefile.in: Regenerate.
+ * configure: Likewise.
+
+2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext-tbl.h (EXTINSN2OPF): Define.
+ (EXTINSN2OP): Use EXTINSN2OPF.
+ (bspeekm, bspop, modapp): New extension instructions.
+ * arc-opc.c (F_DNZ_ND): Define.
+ (F_DNZ_D): Likewise.
+ (F_SIZEB1): Changed.
+ (C_DNZ_D): Define.
+ (C_HARD): Changed.
+ * arc-tbl.h (dbnz): New instruction.
+ (prealloc): Allow it for ARC EM.
+ (xbfu): Likewise.
+
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.c (print_immediate_offset_address): Print spaces
projects / deliverable / binutils-gdb.git / blobdiff