-2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
- (SYMTAB_AVAILABLE): Removed.
- (#include "elf/aarch64.h): Ditto.
-
-2013-06-17 Catherine Moore <clm@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
- Chao-Ying Fu <fu@mips.com>
-
- * micromips-opc.c (EVA): Define.
- (TLBINV): Define.
- (micromips_opcodes): Add EVA opcodes.
- * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
- (print_insn_args): Handle EVA offsets.
- (print_insn_micromips): Likewise.
- * mips-opc.c (EVA): Define.
- (TLBINV): Define.
- (mips_builtin_opcodes): Add EVA opcodes.
-
-2013-06-17 Alan Modra <amodra@gmail.com>
-
- * Makefile.am (mips-opc.lo): Add rules to create automatic
- dependency files. Pass archdefs.
- (micromips-opc.lo, mips16-opc.lo): Likewise.
- * Makefile.in: Regenerate.
-
-2013-06-14 DJ Delorie <dj@redhat.com>
-
- * rx-decode.opc (rx_decode_opcode): Bit operations on
- registers are 32-bit operations, not 8-bit operations.
- * rx-decode.c: Regenerate.
-
-2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
-
- * micromips-opc.c (IVIRT): New define.
- (IVIRT64): New define.
- (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
- tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
-
- * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
- dmtgc0 to print cp0 names.
-
-2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
-
- * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
- argument.
-
-2013-06-08 Catherine Moore <clm@codesourcery.com>
- Richard Sandiford <rdsandiford@googlemail.com>
-
- * micromips-opc.c (D32, D33, MC): Update definitions.
- (micromips_opcodes): Initialize ase field.
- * mips-dis.c (mips_arch_choice): Add ase field.
- (mips_arch_choices): Initialize ase field.
- (set_default_mips_dis_options): Declare and setup mips_ase.
- * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
- MT32, MC): Update definitions.
- (mips_builtin_opcodes): Initialize ase field.
-
-2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
-
- * s390-opc.txt (flogr): Require a register pair destination.
-
-2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
- instruction format.
-
-2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
-
- * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
-
-2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
- * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
- XLS_MASK, PPCVSX2): New defines.
- (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
- fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
- mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
- mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
- mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
- vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
- vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
- vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
- vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
- vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
- vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
- vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
- vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
- vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
- xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
- xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
- xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
- xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
- <lxvx, stxvx>: New extended mnemonics.
-
-2013-05-17 Alan Modra <amodra@gmail.com>
-
- * ia64-raw.tbl: Replace non-ASCII char.
- * ia64-waw.tbl: Likewise.
- * ia64-asmtab.c: Regenerate.
-
-2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
-
- * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
- * i386-init.h: Regenerated.
-
-2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
- * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
- check from [0, 255] to [-128, 255].
-
-2013-05-09 Andrew Pinski <apinski@cavium.com>
-
- * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
- Add INSN_VIRT and INSN_VIRT64 to mips64r2.
- (parse_mips_dis_option): Handle the virt option.
- (print_insn_args): Handle "+J".
- (print_mips_disassembler_options): Print out message about virt64.
- * mips-opc.c (IVIRT): New define.
- (IVIRT64): New define.
- (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
- tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
- Move rfe to the bottom as it conflicts with tlbgp.
-
-2013-05-09 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (extract_vlesi): Properly sign extend.
- (extract_vlensi): Likewise. Comment reason for setting invalid.
-
-2013-05-02 Nick Clifton <nickc@redhat.com>
-
- * msp430-dis.c: Add support for MSP430X instructions.
-
-2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
-
- * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
- to "eccinj".
-
-2013-04-17 Wei-chen Wang <cole945@gmail.com>
-
- PR binutils/15369
- * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
- of CGEN_CPU_ENDIAN.
- (hash_insns_list): Likewise.
-
-2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
-
- * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
- warning workaround.
-
-2013-04-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
- * i386-tbl.h: Re-generate.
-
-2013-04-06 David S. Miller <davem@davemloft.net>
-
- * sparc-dis.c (compare_opcodes): When encountering multiple aliases
- of an opcode, prefer the one with F_PREFERRED set.
- * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
- lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
- ops. Make 64-bit VIS logical ops have "d" suffix in their names,
- mark existing mnenomics as aliases. Add "cc" suffix to edge
- instructions generating condition codes, mark existing mnenomics
- as aliases. Add "fp" prefix to VIS compare instructions, mark
- existing mnenomics as aliases.
-
-2013-04-03 Nick Clifton <nickc@redhat.com>
-
- * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
- destination address by subtracting the operand from the current
- address.
- * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
- a positive value in the insn.
- (extract_u16_loop): Do not negate the returned value.
- (D16_LOOP): Add V850_INVERSE_PCREL flag.
-
- (ceilf.sw): Remove duplicate entry.
- (cvtf.hs): New entry.
- (cvtf.sh): Likewise.
- (fmaf.s): Likewise.
- (fmsf.s): Likewise.
- (fnmaf.s): Likewise.
- (fnmsf.s): Likewise.
- (maddf.s): Restrict to E3V5 architectures.
- (msubf.s): Likewise.
- (nmaddf.s): Likewise.
- (nmsubf.s): Likewise.
-
-2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (get_sib): Add the sizeflag argument. Properly
- check address mode.
- (print_insn): Pass sizeflag to get_sib.
-
-2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
-
- PR binutils/15068
- * tic6x-dis.c: Add support for displaying 16-bit insns.
-
-2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
-
- PR gas/15095
- * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
- individual msb and lsb halves in src1 & src2 fields. Discard the
- src1 (lsb) value and only use src2 (msb), discarding bit 0, to
- follow what Ti SDK does in that case as any value in the src1
- field yields the same output with SDK disassembler.
-
-2013-03-12 Michael Eager <eager@eagercon.com>
-
- * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
-
-2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
-
-2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
-
-2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
-
-2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
- (thumb32_opcodes): Likewise.
- (print_insn_thumb32): Handle 'S' control char.
-
-2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
-
- * lm32-desc.c: Regenerate.
-
-2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-reg.tbl (riz): Add RegRex64.
- * i386-tbl.h: Regenerated.
-
-2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
- (aarch64_feature_crc): New static.
- (CRC): New macro.
- (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
- crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
- * aarch64-asm-2.c: Re-generate.
- * aarch64-dis-2.c: Ditto.
- * aarch64-opc-2.c: Ditto.
-
-2013-02-27 Alan Modra <amodra@gmail.com>
-
- * rl78-decode.opc (rl78_decode_opcode): Fix typo.
- * rl78-decode.c: Regenerate.
-
-2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
-
- * rl78-decode.opc: Fix encoding of DIVWU insn.
- * rl78-decode.c: Regenerate.
-
-2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/15159
- * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
-
- * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
- (cpu_flags): Add CpuSMAP.
-
- * i386-opc.h (CpuSMAP): New.
- (i386_cpu_flags): Add cpusmap.
-
- * i386-opc.tbl: Add clac and stac.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
-
- * metag-dis.c: Initialize outf->bytes_per_chunk to 4
- which also makes the disassembler output be in little
- endian like it should be.
-
-2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
- fields to NULL.
- (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
-
-2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
-
- * mips-dis.c (is_compressed_mode_p): Only match symbols from the
- section disassembled.
-
-2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * arm-dis.c: Update strht pattern.
-
-2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
-
- * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
- single-float. Disable ll, lld, sc and scd for EE. Disable the
- trunc.w.s macro for EE.
-
-2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
- Andrew Jenner <andrew@codesourcery.com>
-
- Based on patches from Altera Corporation.
-
- * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
- nios2-opc.c.
- * Makefile.in: Regenerated.
- * configure.in: Add case for bfd_nios2_arch.
- * configure: Regenerated.
- * disassemble.c (ARCH_nios2): Define.
- (disassembler): Add case for bfd_arch_nios2.
- * nios2-dis.c: New file.
- * nios2-opc.c: New file.
-
-2013-02-04 Alan Modra <amodra@gmail.com>
+2014-02-10 Alan Modra <amodra@gmail.com>
* po/POTFILES.in: Regenerate.
- * rl78-decode.c: Regenerate.
- * rx-decode.c: Regenerate.
-
-2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
- ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
- * aarch64-asm.c (convert_xtl_to_shll): New function.
- (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
- calling convert_xtl_to_shll.
- * aarch64-dis.c (convert_shll_to_xtl): New function.
- (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
- calling convert_shll_to_xtl.
- * aarch64-gen.c: Update copyright year.
- * aarch64-asm-2.c: Re-generate.
- * aarch64-dis-2.c: Re-generate.
- * aarch64-opc-2.c: Re-generate.
-
-2013-01-24 Nick Clifton <nickc@redhat.com>
-
- * v850-dis.c: Add support for e3v5 architecture.
- * v850-opc.c: Likewise.
-
-2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
-
- * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
- * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
- * aarch64-opc.c (operand_general_constraint_met_p): For
- AARCH64_MOD_LSL, move the range check on the shift amount before the
- alignment check; change to call set_sft_amount_out_of_range_error
- instead of set_imm_out_of_range_error.
- * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
- (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
- 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
- SIMD_IMM_SFT.
-
-2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2013-01-15 Nick Clifton <nickc@redhat.com>
-
- * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
- values.
- * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
-
-2013-01-14 Will Newton <will.newton@imgtec.com>
-
- * metag-dis.c (REG_WIDTH): Increase to 64.
-
-2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
- * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
- XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
- (SH6): Update.
- <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
- "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
- "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
- <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
-
-2013-01-10 Will Newton <will.newton@imgtec.com>
-
- * Makefile.am: Add Meta.
- * configure.in: Add Meta.
- * disassemble.c: Add Meta support.
- * metag-dis.c: New file.
- * Makefile.in: Regenerate.
- * configure: Regenerate.
-
-2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
-
- * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
- (match_opcode): Rename to cr16_match_opcode.
-
-2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
-
- * mips-dis.c: Add names for CP0 registers of r5900.
- * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
- instructions sq and lq.
- Add support for MIPS r5900 CPU.
- Add support for 128 bit MMI (Multimedia Instructions).
- Add support for EE instructions (Emotion Engine).
- Disable unsupported floating point instructions (64 bit and
- undefined compare operations).
- Enable instructions of MIPS ISA IV which are supported by r5900.
- Disable 64 bit co processor instructions.
- Disable 64 bit multiplication and division instructions.
- Disable instructions for co-processor 2 and 3, because these are
- not supported (preparation for later VU0 support (Vector Unit)).
- Disable cvt.w.s because this behaves like trunc.w.s and the
- correct execution can't be ensured on r5900.
- Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
- will confuse less developers and compilers.
+ * po/opcodes.pot: Regenerate.
-2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
+2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
+ Jan Beulich <jbeulich@suse.com>
- * aarch64-opc.c (aarch64_print_operand): Change to print
- AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
- in comment.
- * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
- from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
- OP_MOV_IMM_WIDE.
+ PR binutils/16490
+ * i386-dis.c (OP_E_memory): Fix shift computation for
+ vex_vsib_q_w_dq_mode.
-2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
+2014-01-09 Bradley Nelson <bradnelson@google.com>
+ Roland McGrath <mcgrathr@google.com>
- * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
- PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
+ * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
+ last_rex_prefix is -1.
-2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
+2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
- * i386-gen.c (process_copyright): Update copyright year to 2013.
+ * i386-gen.c (process_copyright): Update copyright year to 2014.
-2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
+2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
- * cr16-dis.c (match_opcode,make_instruction): Remove static
- declaration.
- (dwordU,wordU): Moved typedefs to opcode/cr16.h
- (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
+ * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
-For older changes see ChangeLog-2012
+For older changes see ChangeLog-2013
\f
-Copyright (C) 2013 Free Software Foundation, Inc.
+Copyright (C) 2014 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff