+2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
+
+2017-04-21 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21380
+ * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
+ LD3R and LD4R.
+
+2017-04-13 Alan Modra <amodra@gmail.com>
+
+ * epiphany-desc.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * ip2k-desc.c: Regenerate.
+ * iq2000-desc.c: Regenerate.
+ * lm32-desc.c: Regenerate.
+ * m32c-desc.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * mep-desc.c: Regenerate.
+ * mt-desc.c: Regenerate.
+ * or1k-desc.c: Regenerate.
+ * xc16x-desc.c: Regenerate.
+ * xstormy16-desc.c: Regenerate.
+
+2017-04-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
+ PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
+ PPC_OPCODE_TMR for e6500.
+ * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
+ (PPCVEC3): Define as PPC_OPCODE_POWER9.
+ (PPCVSX2): Define as PPC_OPCODE_POWER8.
+ (PPCVSX3): Define as PPC_OPCODE_POWER9.
+ (PPCHTM): Define as PPC_OPCODE_POWER8.
+ (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
+
+2017-04-10 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
+ * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
+ (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
+ removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
+
+2017-04-09 Pip Cet <pipcet@gmail.com>
+
+ * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
+ appropriate floating-point precision directly.
+
+2017-04-07 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
+ lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
+ lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
+ lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
+ vector instructions with E6500 not PPCVEC2.
+
+2017-04-06 Pip Cet <pipcet@gmail.com>
+
+ * Makefile.am: Add wasm32-dis.c.
+ * configure.ac: Add wasm32-dis.c to wasm32 target.
+ * disassemble.c: Add wasm32 disassembler code.
+ * wasm32-dis.c: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
+2017-04-05 Pedro Alves <palves@redhat.com>
+
+ * arc-dis.c (parse_option, parse_disassembler_options): Constify.
+ * arm-dis.c (parse_arm_disassembler_options): Constify.
+ * ppc-dis.c (powerpc_init_dialect): Constify local.
+ * vax-dis.c (parse_disassembler_options): Constify.
+
+2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
+
+ * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
+ RISCV_GP_SYMBOL.
+
+2017-03-30 Pip Cet <pipcet@gmail.com>
+
+ * configure.ac: Add (empty) bfd_wasm32_arch target.
+ * configure: Regenerate
+ * po/opcodes.pot: Regenerate.
+
+2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
+
+ Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
+ OSA2015.
+ * opcodes/sparc-opc.c (asi_table): New ASIs.
+
+2017-03-29 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
+ "raw" option.
+ (lookup_powerpc): Don't special case -1 dialect. Handle
+ PPC_OPCODE_RAW.
+ (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
+ lookup_powerpc call, pass it on second.
+
+2017-03-27 Alan Modra <amodra@gmail.com>
+
+ PR 21303
+ * ppc-dis.c (struct ppc_mopt): Comment.
+ (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
+
+2017-03-27 Rinat Zelig <rinat@mellanox.com>
+
+ * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
+ * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
+ F_NPS_M, F_NPS_CORE, F_NPS_ALL.
+ (insert_nps_misc_imm_offset): New function.
+ (extract_nps_misc imm_offset): New function.
+ (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
+ (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
+
+2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-mkopc.c (main): Remove vx2 check.
+ * s390-opc.txt: Remove vx2 instruction flags.
+
+2017-03-21 Rinat Zelig <rinat@mellanox.com>
+
+ * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
+ * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
+ (insert_nps_imm_offset): New function.
+ (extract_nps_imm_offset): New function.
+ (insert_nps_imm_entry): New function.
+ (extract_nps_imm_entry): New function.
+
+2017-03-17 Alan Modra <amodra@gmail.com>
+
+ PR 21248
+ * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
+ mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
+ those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
+
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
+ <c.andi>: Likewise.
+ <c.addiw> Likewise.
+
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
+
+2017-03-13 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
+ <srl> Likewise.
+ <srai> Likewise.
+ <sra> Likewise.
+
+2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace S with Load.
+ * i386-opc.h (S): Removed.
+ (Load): New.
+ (i386_opcode_modifier): Replace s with load.
+ * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
+ and {evex}. Replace S with Load.
+ * i386-tbl.h: Regenerated.
+
+2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Use CpuCET on rdsspq.
+ * i386-tbl.h: Regenerated.
+
+2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
+ <vsx>: Do not use PPC_OPCODE_VSX3;
+
+2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
+
+2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_0F1E_MOD_3): New enum.
+ (MOD_0F1E_PREFIX_1): Likewise.
+ (MOD_0F38F5_PREFIX_2): Likewise.
+ (MOD_0F38F6_PREFIX_0): Likewise.
+ (RM_0F1E_MOD_3_REG_7): Likewise.
+ (PREFIX_MOD_0_0F01_REG_5): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
+ (PREFIX_0F1E): Likewise.
+ (PREFIX_MOD_0_0FAE_REG_5): Likewise.
+ (PREFIX_0F38F5): Likewise.
+ (dis386_twobyte): Use PREFIX_0F1E.
+ (reg_table): Add REG_0F1E_MOD_3.
+ (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
+ PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
+ PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
+ (three_byte_table): Use PREFIX_0F38F5.
+ (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
+ Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
+ (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
+ RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
+ PREFIX_MOD_3_0F01_REG_5_RM_2.
+ * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
+ (cpu_flags): Add CpuCET.
+ * i386-opc.h (CpuCET): New enum.
+ (CpuUnused): Commented out.
+ (i386_cpu_flags): Add cpucet.
+ * i386-opc.tbl: Add Intel CET instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2017-03-06 Alan Modra <amodra@gmail.com>
+
+ PR 21124
+ * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
+ (extract_raq, extract_ras, extract_rbx): New functions.
+ (powerpc_operands): Use opposite corresponding insert function.
+ (Q_MASK): Define.
+ (powerpc_opcodes): Apply Q_MASK to all quad insns with even
+ register restriction.
+
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
* disassemble.c Include "safe-ctype.h".
projects / deliverable / binutils-gdb.git / blobdiff