X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d412db9eea1b0da4b6d5a01dd0ddfb579ab2618b..a076189c132fece2f57763e470c97906cf26db26 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,32 @@
+2017-07-05  Borislav Petkov  <bp@suse.de>
+
+       * i386-dis.c: Enable ModRM.reg /6 aliases.
+
+2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+        * opcodes/arm-dis.c: Support MVFR2 in disassembly
+        with vmrs and vmsr.
+
+2017-07-04  Tristan Gingold  <gingold@adacore.com>
+
+       * configure: Regenerate.
+
+2017-07-03  Tristan Gingold  <gingold@adacore.com>
+
+       * po/opcodes.pot: Regenerate.
+
+2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
+       entries to the MSA ASE instruction block.
+
+2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
+           Maciej W. Rozycki  <macro@imgtec.com>
+
+       * micromips-opc.c (XPA, XPAVZ): New macros.
+       (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
+       "mthgc0".
+
 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
            Maciej W. Rozycki  <macro@imgtec.com>
 
@@ -49,7 +78,7 @@
 
 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
            Matthew Fortune  <matthew.fortune@imgtec.com>
-           Andrew Bennett <andrew.bennett@imgtec.com>
+           Andrew Bennett  <andrew.bennett@imgtec.com>
 
        * mips-formats.h (INT_BIAS): New macro.
        (INT_ADJ): Redefine in INT_BIAS terms.