-2017-11-16 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
- (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
- (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
- (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
- (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
- (ldapur, ldapursw, stlur): New.
- * aarch64-dis-2.c: Regenerate.
+2018-09-13 Jan Beulich <jbeulich@suse.com>
-2017-11-16 Jan Beulich <jbeulich@suse.com>
+ * i386-opc.tbl: Drop IgnoreSize from AVX insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
- (get_valid_dis386): Never flag bad opcode when
- vex.register_specifier is beyond 7. Always store all four
- bits of it. Move 16-/32-bit override in EVEX handling after
- all to be overridden bits have been set.
- (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
- Use rex to determine GPR register set.
- (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
- OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
+2018-09-13 Jan Beulich <jbeulich@suse.com>
-2017-11-15 Jan Beulich <jbeulich@suse.com>
+ * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
+ * i386-tbl.h: Re-generate.
- * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
- determine GPR register set.
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
+ * i386-tbl.h: Re-generate.
-2017-11-15 Jan Beulich <jbeulich@suse.com>
+2018-09-13 Jan Beulich <jbeulich@suse.com>
- * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
- (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
- (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
- pass.
- (OP_REG_VexI4): Drop low 4 bits check.
+ * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
+ * i386-tbl.h: Re-generate.
-2017-11-15 Jan Beulich <jbeulich@suse.com>
+2018-09-13 Jan Beulich <jbeulich@suse.com>
- * i386-reg.tbl (axl): Remove Acc and Byte.
+ * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
+ meaningless.
* i386-tbl.h: Re-generate.
-2017-11-14 Jan Beulich <jbeulich@suse.com>
+2018-09-13 Jan Beulich <jbeulich@suse.com>
- * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
- (vex_len_table): Use VPCOM.
+ * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
+ meaningless.
+ * i386-tbl.h: Re-generate.
-2017-11-14 Jan Beulich <jbeulich@suse.com>
+2018-09-13 Jan Beulich <jbeulich@suse.com>
- * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
- (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
- * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
- vpcmpw): Move up.
- (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
- vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
- vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
- vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
- vpcmpnltuw): New.
+ * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
+ meaningless.
* i386-tbl.h: Re-generate.
-2017-11-14 Jan Beulich <jbeulich@suse.com>
+2018-09-13 Jan Beulich <jbeulich@suse.com>
- * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
- smov, ssca, stos, ssto, xlat): Drop Disp*.
+ * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
* i386-tbl.h: Re-generate.
-2017-11-13 Jan Beulich <jbeulich@suse.com>
+2018-09-13 Jan Beulich <jbeulich@suse.com>
- * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
- xsaveopt64): Add No_qSuf.
+ * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
* i386-tbl.h: Re-generate.
-2017-11-09 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
- dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
- cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
- sder32_el2, vncr_el2.
- (aarch64_sys_reg_supported_p): Likewise.
- (aarch64_pstatefields): Add dit register.
- (aarch64_pstatefield_supported_p): Likewise.
- (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
- vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
- vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
- rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
- rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
- ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
- rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
-
-2017-11-09 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
- (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
- (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
- (QL_STLW, QL_STLX): New.
-
-2017-11-09 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-asm.h (ins_addr_offset): New.
- * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
- (aarch64_ins_addr_offset): New.
- * aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_addr_offset): New.
- * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
- (aarch64_ext_addr_offset): New.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
- FLD_imm4_2 and FLD_SM3_imm2.
- * aarch64-opc.c (fields): Add FLD_imm6_2,
- FLD_imm4_2 and FLD_SM3_imm2.
- (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
- (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
- AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
- * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
- * aarch64-tbl.h
- (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
-
-2017-11-09 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-tbl.h
- (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
- (aarch64_feature_sm4, aarch64_feature_sha3): New.
- (aarch64_feature_fp_16_v8_2): New.
- (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
- (V8_4_INSN, CRYPTO_V8_2_INSN): New.
- (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
-
-2017-11-08 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
- (aarch64_feature_sha2, aarch64_feature_aes): New.
- (SHA2, AES): New.
- (AES_INSN, SHA2_INSN): New.
- (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
- (sha1h, sha1su1, sha256su0, sha1c, sha1p,
- sha1m, sha1su0, sha256h, sha256h2, sha256su1):
- Change to SHA2_INS.
-
-2017-11-08 Jiong Wang <jiong.wang@arm.com>
- Tamar Christina <tamar.christina@arm.com>
-
- * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
- FP16 instructions, including vfmal.f16 and vfmsl.f16.
-
-2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
-
- * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
-
-2017-11-07 Alan Modra <amodra@gmail.com>
-
- * opintl.h: Formatting, comment fixes.
- (gettext, ngettext): Redefine when ENABLE_NLS.
- (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
- (_): Define using gettext.
- (textdomain, bindtextdomain): Use safer "do nothing".
-
-2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (print_hex): New variable.
- (parse_option): Check for hex option.
- (print_insn_arc): Use hexadecimal representation for short
- immediate values when requested.
- (print_arc_disassembler_options): Add hex option to the list.
-
-2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
- (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
- (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
- (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
- (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
- (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
- (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
- (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
- (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
- (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
- (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
- (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
- (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
- (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
- (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
- (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
- (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
- (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
- (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
- Changed opcodes.
- (prealloc, prefetch*): Place them before ld instruction.
- * arc-opc.c (skip_this_opcode): Add ARITH class.
-
-2017-10-25 Alan Modra <amodra@gmail.com>
-
- PR 22348
- * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
- (cr16_words, cr16_allWords, processing_argument_number): Likewise.
- (imm4flag, size_changed): Likewise.
- * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
- (words, allWords, processing_argument_number): Likewise.
- (cst4flag, size_changed): Likewise.
- * crx-opc.c (crx_cst4_map): Rename from cst4_map.
- (crx_cst4_maps): Rename from cst4_maps.
- (crx_no_op_insn): Rename from no_op_insn.
-
-2017-10-24 Andrew Waterman <andrew@sifive.com>
-
- * riscv-opc.c (match_c_addi16sp) : New function.
- (match_c_addi4spn): New function.
- (match_c_lui): Don't allow 0-immediate encodings.
- (riscv_opcodes) <addi>: Use the above functions.
- <add>: Likewise.
- <c.addi4spn>: Likewise.
- <c.addi16sp>: Likewise.
-
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-init.h: Regenerate
- * i386-tbl.h: Likewise
-
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
- (enum): Add EVEX_W_0F3854_P_2.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
- CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_BITALG.
- * i386-opc.h (enum): Add CpuAVX512_BITALG.
- (i386_cpu_flags): Add cpuavx512_bitalg..
- * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Likewise.
+2018-09-13 Jan Beulich <jbeulich@suse.com>
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
+ * i386-tbl.h: Re-generate.
- * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
- CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_VNNI.
- * i386-opc.h (enum): Add CpuAVX512_VNNI.
- (i386_cpu_flags): Add cpuavx512_vnni.
- * i386-opc.tbl Add Intel AVX512_VNNI instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Likewise.
+2018-09-13 Jan Beulich <jbeulich@suse.com>
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
- (enum): Remove VEX_LEN_0F3A44_P_2.
- (vex_len_table): Ditto.
- (enum): Remove VEX_W_0F3A44_P_2.
- (vew_w_table): Ditto.
- (prefix_table): Adjust instructions (see prefixes above).
- * i386-dis-evex.h (evex_table):
- Add new instructions (see prefixes above).
- * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
- (bitfield_cpu_flags): Ditto.
- * i386-opc.h (enum): Ditto.
- (i386_cpu_flags): Ditto.
- (CpuUnused): Comment out to avoid zero-width field problem.
- * i386-opc.tbl (vpclmulqdq): New instruction.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
-
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
- PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
- (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
- VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
- (vex_len_table): Ditto.
- (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
- VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
- (vew_w_table): Ditto.
- (prefix_table): Adjust instructions (see prefixes above).
- * i386-dis-evex.h (evex_table):
- Add new instructions (see prefixes above).
- * i386-gen.c (cpu_flag_init): Add VAES.
- (bitfield_cpu_flags): Ditto.
- * i386-opc.h (enum): Ditto.
- (i386_cpu_flags): Ditto.
- * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
-
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
- PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
- PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
- (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
- EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
- (prefix_table): Updated (see prefixes above).
- (three_byte_table): Likewise.
- (vex_w_table): Likewise.
- * i386-dis-evex.h: Likewise.
- * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
- (cpu_flags): Add CpuGFNI.
- * i386-opc.h (enum): Add CpuGFNI.
- (i386_cpu_flags): Add cpugfni.
- * i386-opc.tbl: Add Intel GFNI instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Likewise.
+ * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
+ (vpbroadcastw, rdpid): Drop NoRex64.
+ * i386-tbl.h: Re-generate.
-2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
-
- * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
- Define EXbScalar and EXwScalar for OP_EX.
- (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
- PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
- PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
- PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
- (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
- EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
- EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
- EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
- (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
- (OP_E_memory): Likewise.
- * i386-dis-evex.h: Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
- CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_VBMI2.
- * i386-opc.h (enum): Add CpuAVX512_VBMI2.
- (i386_cpu_flags): Add cpuavx512_vbmi2.
- * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Likewise.
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
+ store templates, adding D.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
+ movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
+ movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
+ vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
+ vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
+ Fold load and store templates where possible, adding D. Drop
+ IgnoreSize where it was pointlessly present. Drop redundant
+ *word.
+ * i386-tbl.h: Re-generate.
+
+2018-09-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
+ (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
+ (intel_operand_size): Handle v_bndmk_mode.
+ (OP_E_memory): Likewise. Produce (bad) when also riprel.
-2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
+2018-09-08 John Darrington <john@darrington.wattle.id.au>
- * visium-dis.c (disassem_class1) <case 0>: Print the operands.
+ * disassemble.c (ARCH_s12z): Define if ARCH_all.
-2017-10-12 James Bowman <james.bowman@ftdichip.com>
+2018-08-31 Kito Cheng <kito@andestech.com>
- * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
- * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
- K15. Add jmpix pattern.
+ * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
+ compressed floating point instructions.
-2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+2018-08-30 Kito Cheng <kito@andestech.com>
- * s390-opc.txt (prno, tpei, irbm): New instructions added.
+ * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
+ riscv_opcode.xlen_requirement.
+ * riscv-opc.c (riscv_opcodes): Update for struct change.
-2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
+2018-08-29 Martin Aberg <maberg@gaisler.com>
- * s390-opc.c (INSTR_SI_RD): New macro.
- (INSTR_S_RD): Adjust example instruction.
- * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
- SI_RD.
+ * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
+ psr (PWRPSR) instruction.
-2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
- e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
- VLE multimple load/store instructions. Old e_ldm* variants are
- kept as aliases.
- Add missing e_lmvmcsrrw and e_stmvmcsrrw.
+ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
-2017-09-27 Nick Clifton <nickc@redhat.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- PR 22179
- * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
- names for the fmv.x.s and fmv.s.x instructions respectively.
+ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
-2017-09-26 do <do@nerilex.org>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- PR 22123
- * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
- be used on CPUs that have emacs support.
+ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
+ loongson3a as an alias of gs464 for compatibility.
+ * mips-opc.c (mips_opcodes): Change Comments.
-2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
+ * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
+ option.
+ (print_mips_disassembler_options): Document -M loongson-ext.
+ * mips-opc.c (LEXT2): New macro.
+ (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
-2017-09-09 Kamil Rytarowski <n54@gmx.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * nds32-asm.c: Rename __BIT() to N32_BIT().
- * nds32-asm.h: Likewise.
- * nds32-dis.c: Likewise.
+ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
+ descriptors.
+ (parse_mips_ase_option): Handle -M loongson-ext option.
+ (print_mips_disassembler_options): Document -M loongson-ext.
+ * mips-opc.c (IL3A): Delete.
+ * mips-opc.c (LEXT): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
+ instructions.
-2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
- * i386-dis.c (last_active_prefix): Removed.
- (ckprefix): Don't set last_active_prefix.
- (NOTRACK_Fixup): Don't check last_active_prefix.
+ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
+ descriptors.
+ (parse_mips_ase_option): Handle -M loongson-cam option.
+ (print_mips_disassembler_options): Document -M loongson-cam.
+ * mips-opc.c (LCAM): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
+ instructions.
-2017-08-31 Nick Clifton <nickc@redhat.com>
+2018-08-21 Alan Modra <amodra@gmail.com>
- * po/fr.po: Updated French translation.
+ * ppc-dis.c (operand_value_powerpc): Init "invalid".
+ (skip_optional_operands): Count optional operands, and update
+ ppc_optional_operand_value call.
+ * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
+ (extract_vlensi): Likewise.
+ (extract_fxm): Return default value for missing optional operand.
+ (extract_ls, extract_raq, extract_tbr): Likewise.
+ (insert_sxl, extract_sxl): New functions.
+ (insert_esync, extract_esync): Remove Power9 handling and simplify.
+ (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
+ flag and extra entry.
+ (powerpc_operands <SXL>): Likewise, and use insert_sxl and
+ extract_sxl.
-2017-08-31 James Bowman <james.bowman@ftdichip.com>
+2018-08-20 Alan Modra <amodra@gmail.com>
- * ft32-dis.c (print_insn_ft32): Correct display of non-address
+ * sh-opc.h (MASK): Simplify.
+
+2018-08-18 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-dis.c (bm_decode): Deal with cases where the mode is
+ BM_RESERVED0 or BM_RESERVED1
+ (bm_rel_decode, bm_n_bytes): Ditto.
+
+2018-08-18 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z.h: Delete.
+
+2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
+ address with the addr32 prefix and without base nor index
+ registers.
+
+2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
+ CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
+ CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
+ (cpu_flags): Add CpuCMOV and CpuFXSR.
+ * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
+ fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h: Update auxiliary registers.
+
+2018-08-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
+ (RegIP, RegIZ): Define.
+ * i386-reg.tbl: Adjust comments.
+ (rip): Use Qword instead of BaseIndex. Use RegIP.
+ (eip): Use Dword instead of BaseIndex. Use RegIP.
+ (riz): Add Qword. Use RegIZ.
+ (eiz): Add Dword. Use RegIZ.
+ * i386-tbl.h: Re-generate.
+
+2018-08-03 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
+ pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
+ vpmovzxdq, vpmovzxwd): Remove NoRex64.
+ * i386-tbl.h: Re-generate.
+
+2018-08-03 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_types): Remove Mem field.
+ * i386-opc.h (union i386_operand_type): Remove mem field.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2018-08-01 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
+2018-07-31 Nick Clifton <nickc@redhat.com>
+
+ * po/sv.po: Updated Swedish translation.
+
+2018-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2018-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (ZEROING_MASKING) Rename to ...
+ (DYNAMIC_MASKING): ... this. Adjust comment.
+ * i386-opc.tbl (MaskingMorZ): Define.
+ (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
+ vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
+ vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
+ vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
+ vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
+ vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
+ vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
+ vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
+ vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
+
+2018-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Use element rather than vector size for AVX512*
+ scatter/gather insns.
+ * i386-tbl.h: Re-generate.
+
+2018-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
+ (cpu_flags): Drop CpuVREX.
+ * i386-opc.h (CpuVREX): Delete.
+ (union i386_cpu_flags): Remove cpuvrex.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2018-07-30 Jim Wilson <jimw@sifive.com>
+
+ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
fields.
+ * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
-2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
- Edmar Wienskoski <edmar.wienskoski@nxp.com>
-
- * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
- PPC_OPCODE_EFS2 flag to "e200z4" entry.
- New entries efs2 and spe2.
- Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
- (SPE2_OPCD_SEGS): New macro.
- (spe2_opcd_indices): New.
- (disassemble_init_powerpc): Handle SPE2 opcodes.
- (lookup_spe2): New function.
- (print_insn_powerpc): call lookup_spe2.
- * ppc-opc.c (insert_evuimm1_ex0): New function.
- (extract_evuimm1_ex0): Likewise.
- (insert_evuimm_lt8): Likewise.
- (extract_evuimm_lt8): Likewise.
- (insert_off_spe2): Likewise.
- (extract_off_spe2): Likewise.
- (insert_Ddd): Likewise.
- (extract_Ddd): Likewise.
- (DD): New operand.
- (EVUIMM_LT8): Likewise.
- (EVUIMM_LT16): Adjust.
- (MMMM): New operand.
- (EVUIMM_1): Likewise.
- (EVUIMM_1_EX0): Likewise.
- (EVUIMM_2): Adjust.
- (NNN): New operand.
- (VX_OFF_SPE2): Likewise.
- (BBB): Likewise.
- (DDD): Likewise.
- (VX_MASK_DDD): New mask.
- (HH): New operand.
- (VX_RA_CONST): New macro.
- (VX_RA_CONST_MASK): Likewise.
- (VX_RB_CONST): Likewise.
- (VX_RB_CONST_MASK): Likewise.
- (VX_OFF_SPE2_MASK): Likewise.
- (VX_SPE_CRFD): Likewise.
- (VX_SPE_CRFD_MASK VX): Likewise.
- (VX_SPE2_CLR): Likewise.
- (VX_SPE2_CLR_MASK): Likewise.
- (VX_SPE2_SPLATB): Likewise.
- (VX_SPE2_SPLATB_MASK): Likewise.
- (VX_SPE2_OCTET): Likewise.
- (VX_SPE2_OCTET_MASK): Likewise.
- (VX_SPE2_DDHH): Likewise.
- (VX_SPE2_DDHH_MASK): Likewise.
- (VX_SPE2_HH): Likewise.
- (VX_SPE2_HH_MASK): Likewise.
- (VX_SPE2_EVMAR): Likewise.
- (VX_SPE2_EVMAR_MASK): Likewise.
- (PPCSPE2): Likewise.
- (PPCEFS2): Likewise.
- (vle_opcodes): Add EFS2 and some missing SPE opcodes.
- (powerpc_macros): Map old SPE instructions have new names
- with the same opcodes. Add SPE2 instructions which just are
- mapped to SPE2.
- (spe2_opcodes): Add SPE2 opcodes.
-
-2017-08-23 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c: Formatting and comment fixes. Move insert and
- extract functions earlier, deleting forward declarations.
- (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
- RA_MASK.
-
-2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
-
- * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
-
-2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
- Edmar Wienskoski <edmar.wienskoski@nxp.com>
-
- * ppc-opc.c (insert_evuimm2_ex0): New function.
- (extract_evuimm2_ex0): Likewise.
- (insert_evuimm4_ex0): Likewise.
- (extract_evuimm4_ex0): Likewise.
- (insert_evuimm8_ex0): Likewise.
- (extract_evuimm8_ex0): Likewise.
- (insert_evuimm_lt16): Likewise.
- (extract_evuimm_lt16): Likewise.
- (insert_rD_rS_even): Likewise.
- (extract_rD_rS_even): Likewise.
- (insert_off_lsp): Likewise.
- (extract_off_lsp): Likewise.
- (RD_EVEN): New operand.
- (RS_EVEN): Likewise.
- (RSQ): Adjust.
- (EVUIMM_LT16): New operand.
- (HTM_SI): Adjust.
- (EVUIMM_2_EX0): New operand.
- (EVUIMM_4): Adjust.
- (EVUIMM_4_EX0): New operand.
- (EVUIMM_8): Adjust.
- (EVUIMM_8_EX0): New operand.
- (WS): Adjust.
- (VX_OFF): New operand.
- (VX_LSP): New macro.
- (VX_LSP_MASK): Likewise.
- (VX_LSP_OFF_MASK): Likewise.
- (PPC_OPCODE_LSP): Likewise.
- (vle_opcodes): Add LSP opcodes.
- * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
-
-2017-08-09 Jiong Wang <jiong.wang@arm.com>
-
- * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
- register operands in CRC instructions.
- (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
- comments.
+2018-07-30 Andrew Jenner <andrew@codesourcery.com>
-2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * disassemble.c (disassembler): Mark big and mach with
- ATTRIBUTE_UNUSED.
-
-2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
-
- * disassemble.c (disassembler): Remove arch/mach/endian
- assertions.
-
-2017-07-25 Nick Clifton <nickc@redhat.com>
-
- PR 21739
- * arc-opc.c (insert_rhv2): Use lower case first letter in error
- message.
- (insert_r0): Likewise.
- (insert_r1): Likewise.
- (insert_r2): Likewise.
- (insert_r3): Likewise.
- (insert_sp): Likewise.
- (insert_gp): Likewise.
- (insert_pcl): Likewise.
- (insert_blink): Likewise.
- (insert_ilink1): Likewise.
- (insert_ilink2): Likewise.
- (insert_ras): Likewise.
- (insert_rbs): Likewise.
- (insert_rcs): Likewise.
- (insert_simm3s): Likewise.
- (insert_rrange): Likewise.
- (insert_r13el): Likewise.
- (insert_fpel): Likewise.
- (insert_blinkel): Likewise.
- (insert_pclel): Likewise.
- (insert_nps_bitop_size_2b): Likewise.
- (insert_nps_imm_offset): Likewise.
- (insert_nps_imm_entry): Likewise.
- (insert_nps_size_16bit): Likewise.
- (insert_nps_##NAME##_pos): Likewise.
- (insert_nps_##NAME): Likewise.
- (insert_nps_bitop_ins_ext): Likewise.
- (insert_nps_##NAME): Likewise.
- (insert_nps_min_hofs): Likewise.
- (insert_nps_##NAME): Likewise.
- (insert_nps_rbdouble_64): Likewise.
- (insert_nps_misc_imm_offset): Likewise.
- * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
- option description.
-
-2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
- Jiong Wang <jiong.wang@arm.com>
-
- * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
- correct the print.
- * aarch64-dis-2.c: Regenerated.
-
-2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
-
- * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
- table.
-
-2017-07-20 Nick Clifton <nickc@redhat.com>
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
+ * Makefile.in: Regenerated.
+ * configure.ac: Add C-SKY.
+ * configure: Regenerated.
+ * csky-dis.c: New file.
+ * csky-opc.h: New file.
+ * disassemble.c (ARCH_csky): Define.
+ (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
+ * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
- * po/de.po: Updated German translation.
+2018-07-27 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_sprbat): Correct function parameter and
+ return type.
+ (extract_sprbat): Likewise, variable too.
-2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-regs.h (sec_stat): New aux register.
- (aux_kernel_sp): Likewise.
- (aux_sec_u_sp): Likewise.
- (aux_sec_k_sp): Likewise.
- (sec_vecbase_build): Likewise.
- (nsc_table_top): Likewise.
- (nsc_table_base): Likewise.
- (ersec_stat): Likewise.
- (aux_sec_except): Likewise.
-
-2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-opc.c (extract_uimm12_20): New function.
- (UIMM12_20): New operand.
- (SIMM3_5_S): Adjust.
- * arc-tbl.h (sjli): Add new instruction.
-
-2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
- John Eric Martin <John.Martin@emmicro-us.com>
-
- * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
- (UIMM3_23): Adjust accordingly.
- * arc-regs.h: Add/correct jli_base register.
- * arc-tbl.h (jli_s): Likewise.
-
-2017-07-18 Nick Clifton <nickc@redhat.com>
-
- PR 21775
- * aarch64-opc.c: Fix spelling typos.
- * i386-dis.c: Likewise.
-
-2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
-
- * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
- max_addr_offset and octets variables to size_t.
-
-2017-07-12 Alan Modra <amodra@gmail.com>
-
- * po/da.po: Update from translationproject.org/latest/opcodes/.
- * po/de.po: Likewise.
- * po/es.po: Likewise.
- * po/fi.po: Likewise.
- * po/fr.po: Likewise.
- * po/id.po: Likewise.
- * po/it.po: Likewise.
- * po/nl.po: Likewise.
- * po/pt_BR.po: Likewise.
- * po/ro.po: Likewise.
- * po/sv.po: Likewise.
- * po/tr.po: Likewise.
- * po/uk.po: Likewise.
- * po/vi.po: Likewise.
- * po/zh_CN.po: Likewise.
-
-2017-07-11 Yao Qi <yao.qi@linaro.org>
+2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
Alan Modra <amodra@gmail.com>
- * cgen.sh: Mark generated files read-only.
- * epiphany-asm.c: Regenerate.
- * epiphany-desc.c: Regenerate.
- * epiphany-desc.h: Regenerate.
- * epiphany-dis.c: Regenerate.
- * epiphany-ibld.c: Regenerate.
- * epiphany-opc.c: Regenerate.
- * epiphany-opc.h: Regenerate.
- * fr30-asm.c: Regenerate.
- * fr30-desc.c: Regenerate.
- * fr30-desc.h: Regenerate.
- * fr30-dis.c: Regenerate.
- * fr30-ibld.c: Regenerate.
- * fr30-opc.c: Regenerate.
- * fr30-opc.h: Regenerate.
- * frv-asm.c: Regenerate.
- * frv-desc.c: Regenerate.
- * frv-desc.h: Regenerate.
- * frv-dis.c: Regenerate.
- * frv-ibld.c: Regenerate.
- * frv-opc.c: Regenerate.
- * frv-opc.h: Regenerate.
- * ip2k-asm.c: Regenerate.
- * ip2k-desc.c: Regenerate.
- * ip2k-desc.h: Regenerate.
- * ip2k-dis.c: Regenerate.
- * ip2k-ibld.c: Regenerate.
- * ip2k-opc.c: Regenerate.
- * ip2k-opc.h: Regenerate.
- * iq2000-asm.c: Regenerate.
- * iq2000-desc.c: Regenerate.
- * iq2000-desc.h: Regenerate.
- * iq2000-dis.c: Regenerate.
- * iq2000-ibld.c: Regenerate.
- * iq2000-opc.c: Regenerate.
- * iq2000-opc.h: Regenerate.
- * lm32-asm.c: Regenerate.
- * lm32-desc.c: Regenerate.
- * lm32-desc.h: Regenerate.
- * lm32-dis.c: Regenerate.
- * lm32-ibld.c: Regenerate.
- * lm32-opc.c: Regenerate.
- * lm32-opc.h: Regenerate.
- * lm32-opinst.c: Regenerate.
- * m32c-asm.c: Regenerate.
- * m32c-desc.c: Regenerate.
- * m32c-desc.h: Regenerate.
- * m32c-dis.c: Regenerate.
- * m32c-ibld.c: Regenerate.
- * m32c-opc.c: Regenerate.
- * m32c-opc.h: Regenerate.
- * m32r-asm.c: Regenerate.
- * m32r-desc.c: Regenerate.
- * m32r-desc.h: Regenerate.
- * m32r-dis.c: Regenerate.
- * m32r-ibld.c: Regenerate.
- * m32r-opc.c: Regenerate.
- * m32r-opc.h: Regenerate.
- * m32r-opinst.c: Regenerate.
- * mep-asm.c: Regenerate.
- * mep-desc.c: Regenerate.
- * mep-desc.h: Regenerate.
- * mep-dis.c: Regenerate.
- * mep-ibld.c: Regenerate.
- * mep-opc.c: Regenerate.
- * mep-opc.h: Regenerate.
- * mt-asm.c: Regenerate.
- * mt-desc.c: Regenerate.
- * mt-desc.h: Regenerate.
- * mt-dis.c: Regenerate.
- * mt-ibld.c: Regenerate.
- * mt-opc.c: Regenerate.
- * mt-opc.h: Regenerate.
- * or1k-asm.c: Regenerate.
- * or1k-desc.c: Regenerate.
+ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
+ (powerpc_init_dialect): Handle bfd_mach_ppc_750.
+ * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
+ support disjointed BAT.
+ (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
+ (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
+ (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
+
+2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
+ Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-gen.c (adjust_broadcast_modifier): New function.
+ (process_i386_opcode_modifier): Add an argument for operands.
+ Adjust the Broadcast value based on operands.
+ (output_i386_opcode): Pass operand_types to
+ process_i386_opcode_modifier.
+ (process_i386_opcodes): Pass NULL as operands to
+ process_i386_opcode_modifier.
+ * i386-opc.h (BYTE_BROADCAST): New.
+ (WORD_BROADCAST): Likewise.
+ (DWORD_BROADCAST): Likewise.
+ (QWORD_BROADCAST): Likewise.
+ (i386_opcode_modifier): Expand broadcast to 3 bits.
+ * i386-tbl.h: Regenerated.
+
+2018-07-24 Alan Modra <amodra@gmail.com>
+
+ PR 23430
* or1k-desc.h: Regenerate.
- * or1k-dis.c: Regenerate.
- * or1k-ibld.c: Regenerate.
- * or1k-opc.c: Regenerate.
- * or1k-opc.h: Regenerate.
- * or1k-opinst.c: Regenerate.
- * xc16x-asm.c: Regenerate.
- * xc16x-desc.c: Regenerate.
- * xc16x-desc.h: Regenerate.
- * xc16x-dis.c: Regenerate.
- * xc16x-ibld.c: Regenerate.
- * xc16x-opc.c: Regenerate.
- * xc16x-opc.h: Regenerate.
- * xstormy16-asm.c: Regenerate.
- * xstormy16-desc.c: Regenerate.
- * xstormy16-desc.h: Regenerate.
- * xstormy16-dis.c: Regenerate.
- * xstormy16-ibld.c: Regenerate.
- * xstormy16-opc.c: Regenerate.
- * xstormy16-opc.h: Regenerate.
-
-2017-07-07 Alan Modra <amodra@gmail.com>
-
- * cgen-dis.in: Include disassemble.h, not dis-asm.h.
- * m32c-dis.c: Regenerate.
- * mep-dis.c: Regenerate.
-
-2017-07-05 Borislav Petkov <bp@suse.de>
-
- * i386-dis.c: Enable ModRM.reg /6 aliases.
-
-2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-
- * opcodes/arm-dis.c: Support MVFR2 in disassembly
- with vmrs and vmsr.
-
-2017-07-04 Tristan Gingold <gingold@adacore.com>
- * configure: Regenerate.
+2018-07-24 Jan Beulich <jbeulich@suse.com>
-2017-07-03 Tristan Gingold <gingold@adacore.com>
+ * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
+ vcvtusi2ss, and vcvtusi2sd.
+ * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
+ Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
+ * i386-tbl.h: Re-generate.
- * po/opcodes.pot: Regenerate.
+2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
-2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
- entries to the MSA ASE instruction block.
-
-2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
- Maciej W. Rozycki <macro@imgtec.com>
-
- * micromips-opc.c (XPA, XPAVZ): New macros.
- (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
- "mthgc0".
-
-2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
- Maciej W. Rozycki <macro@imgtec.com>
-
- * micromips-opc.c (I36): New macro.
- (micromips_opcodes): Add "eretnc".
-
-2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
- Andrew Bennett <andrew.bennett@imgtec.com>
-
- * mips-dis.c (mips_calculate_combination_ases): Handle the
- ASE_XPA_VIRT flag.
- (parse_mips_ase_option): New function.
- (parse_mips_dis_option): Factor out ASE option handling to the
- new function. Call `mips_calculate_combination_ases'.
- * mips-opc.c (XPAVZ): New macro.
- (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
- "mfhgc0", "mthc0" and "mthgc0".
-
-2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (mips_calculate_combination_ases): New function.
- (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
- calculation to the new function.
- (set_default_mips_dis_options): Call the new function.
-
-2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
-
- * arc-dis.c (parse_disassembler_options): Use
- FOR_EACH_DISASSEMBLER_OPTION.
-
-2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
-
- * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
- disassembler option strings.
- (parse_cpu_option): Likewise.
-
-2017-06-28 Tamar Christina <tamar.christina@arm.com>
-
- * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
- * aarch64-dis.c (aarch64_ext_reglane): Likewise.
- * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
- (aarch64_feature_dotprod, DOT_INSN): New.
- (udot, sdot): New.
- * aarch64-dis-2.c: Regenerated.
-
-2017-06-28 Jiong Wang <jiong.wang@arm.com>
-
- * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
-
-2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
- Matthew Fortune <matthew.fortune@imgtec.com>
- Andrew Bennett <andrew.bennett@imgtec.com>
-
- * mips-formats.h (INT_BIAS): New macro.
- (INT_ADJ): Redefine in INT_BIAS terms.
- * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
- (mips_print_save_restore): New function.
- (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
- (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
- call.
- (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
- (print_mips16_insn_arg): Call `mips_print_save_restore' for
- OP_SAVE_RESTORE_LIST handling, factored out from here.
- * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
- (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
- (mips_builtin_opcodes): Add "restore" and "save" entries.
- * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
- (IAMR2): New macro.
- (mips16_opcodes): Add "copyw" and "ucopyw" entries.
-
-2017-06-23 Andrew Waterman <andrew@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
- alias; do not mark SLTI instruction as an alias.
-
-2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (RM_0FAE_REG_5): Removed.
- (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
- (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
- (PREFIX_MOD_3_0FAE_REG_5): Likewise.
- (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
- PREFIX_MOD_3_0F01_REG_5_RM_0.
- (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
- PREFIX_MOD_3_0FAE_REG_5.
- (mod_table): Update MOD_0FAE_REG_5.
- (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
- * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
- * i386-tbl.h: Regenerated.
+ * arc-opc.c (extract_w6): Fix extending the sign.
-2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
- * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
- * i386-opc.tbl: Likewise.
- * i386-tbl.h: Regenerated.
+ * arc-tbl.h (vewt): Allow it for ARC EM family.
-2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+2018-07-23 Alan Modra <amodra@gmail.com>
- * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
- and "jmp{&|}".
- (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
- prefix.
+ PR 23419
+ * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
+ opcode variants for mtspr/mfspr encodings.
-2017-06-19 Nick Clifton <nickc@redhat.com>
+2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
+ Maciej W. Rozycki <macro@mips.com>
- PR binutils/21614
- * score-dis.c (score_opcodes): Add sentinel.
+ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
+ loongson3a descriptors.
+ (parse_mips_ase_option): Handle -M loongson-mmi option.
+ (print_mips_disassembler_options): Document -M loongson-mmi.
+ * mips-opc.c (LMMI): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
+ instructions.
-2017-06-16 Alan Modra <amodra@gmail.com>
+2018-07-19 Jan Beulich <jbeulich@suse.com>
- * rx-decode.c: Regenerate.
+ * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
+ vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
+ IgnoreSize and [XYZ]MMword where applicable.
+ * i386-tbl.h: Re-generate.
-2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
+2018-07-19 Jan Beulich <jbeulich@suse.com>
- PR binutils/21594
- * i386-dis.c (OP_E_register): Check valid bnd register.
- (OP_G): Likewise.
+ * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
+ (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
+ (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
+ (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
+ * i386-tbl.h: Re-generate.
-2017-06-15 Nick Clifton <nickc@redhat.com>
+2018-07-19 Jan Beulich <jbeulich@suse.com>
- PR binutils/21595
- * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
- range value.
+ * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
+ AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
+ VPCLMULQDQ templates into their respective AVX512VL counterparts
+ where possible, using Disp8ShiftVL and CheckRegSize instead of
+ Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
-2017-06-15 Nick Clifton <nickc@redhat.com>
+2018-07-19 Jan Beulich <jbeulich@suse.com>
- PR binutils/21588
- * rl78-decode.opc (OP_BUF_LEN): Define.
- (GETBYTE): Check for the index exceeding OP_BUF_LEN.
- (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
- array.
- * rl78-decode.c: Regenerate.
+ * i386-opc.tbl: Fold AVX512DQ templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512BW templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512CD templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
-2017-06-15 Nick Clifton <nickc@redhat.com>
-
- PR binutils/21586
- * bfin-dis.c (gregs): Clip index to prevent overflow.
- (regs): Likewise.
- (regs_lo): Likewise.
- (regs_hi): Likewise.
-
-2017-06-14 Nick Clifton <nickc@redhat.com>
-
- PR binutils/21576
- * score7-dis.c (score_opcodes): Add sentinel.
-
-2017-06-14 Yao Qi <yao.qi@linaro.org>
-
- * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
- * arm-dis.c: Likewise.
- * ia64-dis.c: Likewise.
- * mips-dis.c: Likewise.
- * spu-dis.c: Likewise.
- * disassemble.h (print_insn_aarch64): New declaration, moved from
- include/dis-asm.h.
- (print_insn_big_arm, print_insn_big_mips): Likewise.
- (print_insn_i386, print_insn_ia64): Likewise.
- (print_insn_little_arm, print_insn_little_mips): Likewise.
-
-2017-06-14 Nick Clifton <nickc@redhat.com>
-
- PR binutils/21587
- * rx-decode.opc: Include libiberty.h
- (GET_SCALE): New macro - validates access to SCALE array.
- (GET_PSCALE): New macro - validates access to PSCALE array.
- (DIs, SIs, S2Is, rx_disp): Use new macros.
- * rx-decode.c: Regenerate.
-
-2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
-
-2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
-
- * arc-dis.c (enforced_isa_mask): Declare.
- (cpu_types): Likewise.
- (parse_cpu_option): New function.
- (parse_disassembler_options): Use it.
- (print_insn_arc): Use enforced_isa_mask.
- (print_arc_disassembler_options): Document new options.
-
-2017-05-24 Yao Qi <yao.qi@linaro.org>
-
- * alpha-dis.c: Include disassemble.h, don't include
- dis-asm.h.
- * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
- * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
- * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
- * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
- * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
- * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
- * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
- * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
- * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
- * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
- * moxie-dis.c, msp430-dis.c, mt-dis.c:
- * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
- * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
- * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
- * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
- * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
- * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
- * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
- * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
- * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
- * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
- * z80-dis.c, z8k-dis.c: Likewise.
- * disassemble.h: New file.
-
-2017-05-24 Yao Qi <yao.qi@linaro.org>
-
- * rl78-dis.c (rl78_get_disassembler): If parameter abfd
- is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
-
-2017-05-24 Yao Qi <yao.qi@linaro.org>
-
- * disassemble.c (disassembler): Add arguments a, big and mach.
- Use them.
-
-2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (NOTRACK_Fixup): New.
- (NOTRACK): Likewise.
- (NOTRACK_PREFIX): Likewise.
- (last_active_prefix): Likewise.
- (reg_table): Use NOTRACK on indirect call and jmp.
- (ckprefix): Set last_active_prefix.
- (prefix_name): Return "notrack" for NOTRACK_PREFIX.
- * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
- * i386-opc.h (NoTrackPrefixOk): New.
- (i386_opcode_modifier): Add notrackprefixok.
- * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
- Add notrack.
+ * i386-opc.h (DISP8_SHIFT_VL): New.
+ * i386-opc.tbl (Disp8ShiftVL): Define.
+ (various): Fold AVX512VL templates into their respective
+ AVX512F counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * Makefile.am: Change dependencies and rule for
+ $(srcdir)/i386-init.h.
+ * Makefile.in: Re-generate.
+ * i386-gen.c (process_i386_opcodes): New local variable
+ "marker". Drop opening of input file. Recognize marker and line
+ number directives.
+ * i386-opc.tbl (OPCODE_I386_H): Define.
+ (i386-opc.h): Include it.
+ (None): Undefine.
+
+2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23418
+ * i386-opc.h (Byte): Update comments.
+ (Word): Likewise.
+ (Dword): Likewise.
+ (Fword): Likewise.
+ (Qword): Likewise.
+ (Tbyte): Likewise.
+ (Xmmword): Likewise.
+ (Ymmword): Likewise.
+ (Zmmword): Likewise.
+ * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
+ vcvttps2uqq.
* i386-tbl.h: Regenerated.
-2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
- (X_IMM2): Define.
- (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
- bfd_mach_sparc_v9m8.
- (print_insn_sparc): Handle new operand types.
- * sparc-opc.c (MASK_M8): Define.
- (v6): Add MASK_M8.
- (v6notlet): Likewise.
- (v7): Likewise.
- (v8): Likewise.
- (v9): Likewise.
- (v9a): Likewise.
- (v9b): Likewise.
- (v9c): Likewise.
- (v9d): Likewise.
- (v9e): Likewise.
- (v9v): Likewise.
- (v9m): Likewise.
- (v9andleon): Likewise.
- (m8): Define.
- (HWS_VM8): Define.
- (HWS2_VM8): Likewise.
- (sparc_opcode_archs): Add entry for "m8".
- (sparc_opcodes): Add OSA2017 and M8 instructions
- dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
- fpx{ll,ra,rl}64x,
- ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
- ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
- revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
- stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
- (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
- ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
- ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
- ASI_CORE_SELECT_COMMIT_NHT.
-
-2017-05-18 Alan Modra <amodra@gmail.com>
-
- * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
- * aarch64-dis.c: Likewise.
- * aarch64-gen.c: Likewise.
- * aarch64-opc.c: Likewise.
-
-2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
- Matthew Fortune <matthew.fortune@imgtec.com>
-
- * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
- ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
- (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
- (print_insn_arg) <OP_REG28>: Add handler.
- (validate_insn_args) <OP_REG28>: Handle.
- (print_mips16_insn_arg): Handle MIPS16 instructions that require
- 32-bit encoding and 9-bit immediates.
- (print_insn_mips16): Handle MIPS16 instructions that require
- 32-bit encoding and MFC0/MTC0 operand decoding.
- * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
- <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
- (RD_C0, WR_C0, E2, E2MT): New macros.
- (mips16_opcodes): Add entries for MIPS16e2 instructions:
- GP-relative "addiu" and its "addu" spelling, "andi", "cache",
- "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
- "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
- "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
- "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
- instructions, "swl", "swr", "sync" and its "sync_acquire",
- "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
- "xori", "dmt", "dvpe", "emt" and "evpe". Add split
- regular/extended entries for original MIPS16 ISA revision
- instructions whose extended forms are subdecoded in the MIPS16e2
- ISA revision: "li", "sll" and "srl".
-
-2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
- reference in CP0 move operand decoding.
-
-2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
- type to hexadecimal.
- (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
-
-2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
- "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
- "sync_rmb" and "sync_wmb" as aliases.
- * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
- "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
-
-2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (parse_option): Update quarkse_em option..
- * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
- QUARKSE1.
- (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
-
-2017-05-03 Kito Cheng <kito.cheng@gmail.com>
-
- * riscv-dis.c (print_insn_args): Handle 'Co' operands.
-
-2017-05-01 Michael Clark <michaeljclark@mac.com>
-
- * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
- register.
-
-2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
-
- * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
- and branches and not synthetic data instructions.
-
-2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
-
- * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
-
-2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
+2018-07-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Add entry for
+ ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-07-12 Tamar Christina <tamar.christina@arm.com>
- * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
- * arc-opc.c (insert_r13el): New function.
- (R13_EL): Define.
- * arc-tbl.h: Add new enter/leave variants.
+ PR binutils/23192
+ * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
+ mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
+ umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
+ sqdmulh, sqrdmulh): Use Em16.
-2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
+2018-07-11 Sudakshina Das <sudi.das@arm.com>
- * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
+ * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
+ csdb together with them.
+ (thumb32_opcodes): Likewise.
-2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+2018-07-11 Jan Beulich <jbeulich@suse.com>
- * mips-dis.c (print_mips_disassembler_options): Add
- `no-aliases'.
+ * i386-opc.tbl (monitor, monitorx): Add 64-bit template
+ requiring 32-bit registers as operands 2 and 3. Improve
+ comments.
+ (mwait, mwaitx): Fold templates. Improve comments.
+ OPERAND_TYPE_INOUTPORTREG.
+ * i386-tbl.h: Re-generate.
-2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+2018-07-11 Jan Beulich <jbeulich@suse.com>
- * mips16-opc.c (AL): New macro.
- (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
- of "ld" and "lw" as aliases.
+ * i386-gen.c (operand_type_init): Remove
+ OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
+ OPERAND_TYPE_INOUTPORTREG.
+ * i386-init.h: Re-generate.
-2017-04-24 Tamar Christina <tamar.christina@arm.com>
+2018-07-11 Jan Beulich <jbeulich@suse.com>
- * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
- arguments.
+ * i386-opc.tbl (wrssd, wrussd): Add Dword.
+ (wrssq, wrussq): Add Qword.
+ * i386-tbl.h: Re-generate.
-2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
- Alan Modra <amodra@gmail.com>
+2018-07-11 Jan Beulich <jbeulich@suse.com>
- * ppc-opc.c (ELEV): Define.
- (vle_opcodes): Add se_rfgi and e_sc.
- (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
- for E200Z4.
+ * i386-opc.h: Rename OTMax to OTNum.
+ (OTNumOfUints): Adjust calculation.
+ (OTUnused): Directly alias to OTNum.
-2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
+2018-07-09 Maciej W. Rozycki <macro@mips.com>
- * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
+ * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
+ `reg_xys'.
+ (lea_reg_xys): Likewise.
+ (print_insn_loop_primitive): Rename `reg' local variable to
+ `reg_dxy'.
-2017-04-21 Nick Clifton <nickc@redhat.com>
+2018-07-06 Tamar Christina <tamar.christina@arm.com>
- PR binutils/21380
- * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
- LD3R and LD4R.
+ PR binutils/23242
+ * aarch64-tbl.h (ldarh): Fix disassembly mask.
-2017-04-13 Alan Modra <amodra@gmail.com>
+2018-07-06 Tamar Christina <tamar.christina@arm.com>
- * epiphany-desc.c: Regenerate.
- * fr30-desc.c: Regenerate.
- * frv-desc.c: Regenerate.
- * ip2k-desc.c: Regenerate.
- * iq2000-desc.c: Regenerate.
- * lm32-desc.c: Regenerate.
- * m32c-desc.c: Regenerate.
- * m32r-desc.c: Regenerate.
- * mep-desc.c: Regenerate.
- * mt-desc.c: Regenerate.
- * or1k-desc.c: Regenerate.
- * xc16x-desc.c: Regenerate.
- * xstormy16-desc.c: Regenerate.
+ PR binutils/23369
+ * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
+ vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
-2017-04-11 Alan Modra <amodra@gmail.com>
+2018-07-02 Maciej W. Rozycki <macro@mips.com>
- * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
- PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
- PPC_OPCODE_TMR for e6500.
- * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
- (PPCVEC3): Define as PPC_OPCODE_POWER9.
- (PPCVSX2): Define as PPC_OPCODE_POWER8.
- (PPCVSX3): Define as PPC_OPCODE_POWER9.
- (PPCHTM): Define as PPC_OPCODE_POWER8.
- (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
+ PR tdep/8282
+ * mips-dis.c (mips_option_arg_t): New enumeration.
+ (mips_options): New variable.
+ (disassembler_options_mips): New function.
+ (print_mips_disassembler_options): Reimplement in terms of
+ `disassembler_options_mips'.
+ * arm-dis.c (disassembler_options_arm): Adapt to using the
+ `disasm_options_and_args_t' structure.
+ * ppc-dis.c (disassembler_options_powerpc): Likewise.
+ * s390-dis.c (disassembler_options_s390): Likewise.
-2017-04-10 Alan Modra <amodra@gmail.com>
+2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
- * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
- * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
- (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
- removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
+ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
+ expected result.
+ * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
+ * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
+ * testsuite/ld-arm/tls-longplt.d: Likewise.
-2017-04-09 Pip Cet <pipcet@gmail.com>
+2018-06-29 Tamar Christina <tamar.christina@arm.com>
- * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
- appropriate floating-point precision directly.
+ PR binutils/23192
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+ * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
+ * aarch64-opc.c (operand_general_constraint_met_p,
+ aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
+ smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
+ fmlal2, fmlsl2.
+ (AARCH64_OPERANDS): Add Em2.
+
+2018-06-26 Nick Clifton <nickc@redhat.com>
+
+ * po/uk.po: Updated Ukranian translation.
+ * po/de.po: Updated German translation.
+ * po/pt_BR.po: Updated Brazilian Portuguese translation.
-2017-04-07 Alan Modra <amodra@gmail.com>
+2018-06-26 Nick Clifton <nickc@redhat.com>
- * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
- lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
- lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
- lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
- vector instructions with E6500 not PPCVEC2.
+ * nfp-dis.c: Fix spelling mistake.
-2017-04-06 Pip Cet <pipcet@gmail.com>
+2018-06-24 Nick Clifton <nickc@redhat.com>
- * Makefile.am: Add wasm32-dis.c.
- * configure.ac: Add wasm32-dis.c to wasm32 target.
- * disassemble.c: Add wasm32 disassembler code.
- * wasm32-dis.c: New file.
- * Makefile.in: Regenerate.
* configure: Regenerate.
- * po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
-2017-04-05 Pedro Alves <palves@redhat.com>
+2018-06-24 Nick Clifton <nickc@redhat.com>
- * arc-dis.c (parse_option, parse_disassembler_options): Constify.
- * arm-dis.c (parse_arm_disassembler_options): Constify.
- * ppc-dis.c (powerpc_init_dialect): Constify local.
- * vax-dis.c (parse_disassembler_options): Constify.
+ 2.31 branch created.
-2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
+2018-06-19 Tamar Christina <tamar.christina@arm.com>
- * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
- RISCV_GP_SYMBOL.
+ * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
-2017-03-30 Pip Cet <pipcet@gmail.com>
+2018-06-21 Maciej W. Rozycki <macro@mips.com>
- * configure.ac: Add (empty) bfd_wasm32_arch target.
- * configure: Regenerate
- * po/opcodes.pot: Regenerate.
+ * mips-dis.c (print_mips_disassembler_options): Fix a typo in
+ `-M ginv' option description.
-2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
+2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
- Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
- OSA2015.
- * opcodes/sparc-opc.c (asi_table): New ASIs.
+ PR gas/23305
+ * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
+ la and lla.
-2017-03-29 Alan Modra <amodra@gmail.com>
+2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
- * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
- "raw" option.
- (lookup_powerpc): Don't special case -1 dialect. Handle
- PPC_OPCODE_RAW.
- (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
- lookup_powerpc call, pass it on second.
+ * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
+ * configure.ac: Remove AC_PREREQ.
+ * Makefile.in: Re-generate.
+ * aclocal.m4: Re-generate.
+ * configure: Re-generate.
-2017-03-27 Alan Modra <amodra@gmail.com>
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
- PR 21303
- * ppc-dis.c (struct ppc_mopt): Comment.
- (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
+ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
+ mips64r6 descriptors.
+ (parse_mips_ase_option): Handle -Mginv option.
+ (print_mips_disassembler_options): Document -Mginv.
+ * mips-opc.c (decode_mips_operand) <+\>: New operand format.
+ (GINV): New macro.
+ (mips_opcodes): Define ginvi and ginvt.
-2017-03-27 Rinat Zelig <rinat@mellanox.com>
+2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
+ Faraz Shahbazker <Faraz.Shahbazker@mips.com>
- * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
- * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
- F_NPS_M, F_NPS_CORE, F_NPS_ALL.
- (insert_nps_misc_imm_offset): New function.
- (extract_nps_misc imm_offset): New function.
- (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
- (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
+ * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
+ * mips-opc.c (CRC, CRC64): New macros.
+ (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
+ crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
+ crc32cd for CRC64.
-2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
- * s390-mkopc.c (main): Remove vx2 check.
- * s390-opc.txt: Remove vx2 instruction flags.
+ PR 20319
+ * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+ (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
-2017-03-21 Rinat Zelig <rinat@mellanox.com>
+2018-06-06 Alan Modra <amodra@gmail.com>
- * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
- * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
- (insert_nps_imm_offset): New function.
- (extract_nps_imm_offset): New function.
- (insert_nps_imm_entry): New function.
- (extract_nps_imm_entry): New function.
+ * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
+ setjmp. Move init for some other vars later too.
-2017-03-17 Alan Modra <amodra@gmail.com>
+2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
- PR 21248
- * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
- mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
- those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
+ * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
+ (dis_private): Add new fields for property section tracking.
+ (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
+ (xtensa_instruction_fits): New functions.
+ (fetch_data): Bump minimal fetch size to 4.
+ (print_insn_xtensa): Make struct dis_private static.
+ Load and prepare property table on section change.
+ Don't disassemble literals. Don't disassemble instructions that
+ cross property table boundaries.
-2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
- * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
- <c.andi>: Likewise.
- <c.addiw> Likewise.
+ * configure: Regenerated.
-2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+2018-06-01 Jan Beulich <jbeulich@suse.com>
- * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
+ * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
+ * i386-tbl.h: Re-generate.
-2017-03-13 Andrew Waterman <andrew@sifive.com>
+2018-06-01 Jan Beulich <jbeulich@suse.com>
- * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
- <srl> Likewise.
- <srai> Likewise.
- <sra> Likewise.
+ * i386-opc.tbl (sldt, str): Add NoRex64.
+ * i386-tbl.h: Re-generate.
-2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
+2018-06-01 Jan Beulich <jbeulich@suse.com>
- * i386-gen.c (opcode_modifiers): Replace S with Load.
- * i386-opc.h (S): Removed.
- (Load): New.
- (i386_opcode_modifier): Replace s with load.
- * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
- and {evex}. Replace S with Load.
- * i386-tbl.h: Regenerated.
+ * i386-opc.tbl (invpcid): Add Oword.
+ * i386-tbl.h: Re-generate.
-2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
+2018-06-01 Alan Modra <amodra@gmail.com>
- * i386-opc.tbl: Use CpuCET on rdsspq.
- * i386-tbl.h: Regenerated.
+ * sysdep.h (_bfd_error_handler): Don't declare.
+ * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
+ * rl78-decode.opc: Likewise.
+ * msp430-decode.c: Regenerate.
+ * rl78-decode.c: Regenerate.
-2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
- <vsx>: Do not use PPC_OPCODE_VSX3;
-
-2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
-
-2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (REG_0F1E_MOD_3): New enum.
- (MOD_0F1E_PREFIX_1): Likewise.
- (MOD_0F38F5_PREFIX_2): Likewise.
- (MOD_0F38F6_PREFIX_0): Likewise.
- (RM_0F1E_MOD_3_REG_7): Likewise.
- (PREFIX_MOD_0_0F01_REG_5): Likewise.
- (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
- (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
- (PREFIX_0F1E): Likewise.
- (PREFIX_MOD_0_0FAE_REG_5): Likewise.
- (PREFIX_0F38F5): Likewise.
- (dis386_twobyte): Use PREFIX_0F1E.
- (reg_table): Add REG_0F1E_MOD_3.
- (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
- PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
- PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
- PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
- (three_byte_table): Use PREFIX_0F38F5.
- (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
- Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
- (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
- RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
- PREFIX_MOD_3_0F01_REG_5_RM_2.
- * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
- (cpu_flags): Add CpuCET.
- * i386-opc.h (CpuCET): New enum.
- (CpuUnused): Commented out.
- (i386_cpu_flags): Add cpucet.
- * i386-opc.tbl: Add Intel CET instructions.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
+2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
-2017-03-06 Alan Modra <amodra@gmail.com>
-
- PR 21124
- * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
- (extract_raq, extract_ras, extract_rbx): New functions.
- (powerpc_operands): Use opposite corresponding insert function.
- (Q_MASK): Define.
- (powerpc_opcodes): Apply Q_MASK to all quad insns with even
- register restriction.
-
-2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
-
- * disassemble.c Include "safe-ctype.h".
- (disassemble_init_for_target): Handle s390 init.
- (remove_whitespace_and_extra_commas): New function.
- (disassembler_options_cmp): Likewise.
- * arm-dis.c: Include "libiberty.h".
- (NUM_ELEM): Delete.
- (regnames): Use long disassembler style names.
- Add force-thumb and no-force-thumb options.
- (NUM_ARM_REGNAMES): Rename from this...
- (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
- (get_arm_regname_num_options): Delete.
- (set_arm_regname_option): Likewise.
- (get_arm_regnames): Likewise.
- (parse_disassembler_options): Likewise.
- (parse_arm_disassembler_option): Rename from this...
- (parse_arm_disassembler_options): ...to this. Make static.
- Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
- (print_insn): Use parse_arm_disassembler_options.
- (disassembler_options_arm): New function.
- (print_arm_disassembler_options): Handle updated regnames.
- * ppc-dis.c: Include "libiberty.h".
- (ppc_opts): Add "32" and "64" entries.
- (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
- (powerpc_init_dialect): Add break to switch statement.
- Use new FOR_EACH_DISASSEMBLER_OPTION macro.
- (disassembler_options_powerpc): New function.
- (print_ppc_disassembler_options): Use ARRAY_SIZE.
- Remove printing of "32" and "64".
- * s390-dis.c: Include "libiberty.h".
- (init_flag): Remove unneeded variable.
- (struct s390_options_t): New structure type.
- (options): New structure.
- (init_disasm): Rename from this...
- (disassemble_init_s390): ...to this. Add initializations for
- current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
- (print_insn_s390): Delete call to init_disasm.
- (disassembler_options_s390): New function.
- (print_s390_disassembler_options): Print using information from
- struct 'options'.
- * po/opcodes.pot: Regenerate.
+ * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
+ * i386-init.h : Regenerated.
+
+2018-05-25 Alan Modra <amodra@gmail.com>
+
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
+ insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
+ (insert_bab, extract_bab, insert_btab, extract_btab,
+ insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
+ (BAT, BBA VBA RBS XB6S): Delete macros.
+ (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
+ (BB, BD, RBX, XC6): Update for new macros.
+ (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
+ crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
+ e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
+ * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
+
+2018-05-18 John Darrington <john@darrington.wattle.id.au>
+
+ * Makefile.am: Add support for s12z architecture.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * s12z-dis.c: New file.
+ * s12z.h: New file.
+
+2018-05-18 Alan Modra <amodra@gmail.com>
+
+ * nfp-dis.c: Don't #include libbfd.h.
+ (init_nfp3200_priv): Use bfd_get_section_contents.
+ (nit_nfp6000_mecsr_sec): Likewise.
+
+2018-05-17 Nick Clifton <nickc@redhat.com>
+
+ * po/zh_CN.po: Updated simplified Chinese translation.
+
+2018-05-16 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23109
+ * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
+ * aarch64-dis-2.c: Regenerate.
-2017-02-28 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PCMPESTR_Fixup): New.
- (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
- (prefix_table): Use PCMPESTR_Fixup.
- (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
- PCMPESTR_Fixup.
- (vex_w_table): Delete VPCMPESTR{I,M} entries.
- * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
- Split 64-bit and non-64-bit variants.
- * opcodes/i386-tbl.h: Re-generate.
-
-2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
- (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
- (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
- (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
- (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
- (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
- (OP_SVE_V_HSD): New macros.
- (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
- (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
- (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
- (aarch64_opcode_table): Add new SVE instructions.
- (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
- for rotation operands. Add new SVE operands.
- * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
- (ins_sve_quad_index): Likewise.
- (ins_imm_rotate): Split into...
- (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
- * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
- (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
- functions.
- (aarch64_ins_sve_addr_ri_s4): New function.
- (aarch64_ins_sve_quad_index): Likewise.
- (do_misc_encoding): Handle "MOV Zn.Q, Qm".
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * aarch64-asm.c (opintl.h): Include.
+ (aarch64_ins_sysreg): Enforce read/write constraints.
+ * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
+ * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
+ (F_REG_READ, F_REG_WRITE): New.
+ * aarch64-opc.c (aarch64_print_operand): Generate notes for
+ AARCH64_OPND_SYSREG.
+ (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
+ (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
+ mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
+ id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
+ id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
+ id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
+ mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
+ id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
+ id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
+ id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
+ csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
+ rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
+ mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
+ mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
+ pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
+ * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
+ msr (F_SYS_WRITE), mrs (F_SYS_READ).
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * aarch64-dis.c (no_notes: New.
+ (parse_aarch64_dis_option): Support notes.
+ (aarch64_decode_insn, print_operands): Likewise.
+ (print_aarch64_disassembler_options): Document notes.
+ * aarch64-opc.c (aarch64_print_operand): Support notes.
+
+2018-05-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/21446
+ * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
+ and take error struct.
+ * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
+ aarch64_ins_reglist, aarch64_ins_ldst_reglist,
+ aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
+ aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
+ aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
+ aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
+ aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
+ aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
+ aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
+ aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
+ aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
+ aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
+ aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
+ aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
+ aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
+ aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
+ aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
+ aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
+ aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
+ aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
+ aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
+ aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
+ aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
+ aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
+ aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
+ * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
+ * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
+ aarch64_ext_reglist, aarch64_ext_ldst_reglist,
+ aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
+ aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
+ aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
+ aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
+ aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
+ aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
+ aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
+ aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
+ aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
+ aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
+ aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
+ aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
+ aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
+ aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
+ aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
+ aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
+ aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
+ aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
+ aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
+ aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
+ aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
+ aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
+ aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
+ (determine_disassembling_preference, aarch64_decode_insn,
+ print_insn_aarch64_word, print_insn_data): Take errors struct.
+ (print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
- * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
- (ext_sve_quad_index): Likewise.
- (ext_imm_rotate): Split into...
- (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
- * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
- (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
- functions.
- (aarch64_ext_sve_addr_ri_s4): New function.
- (aarch64_ext_sve_quad_index): Likewise.
- (aarch64_ext_sve_index): Allow quad indices.
- (do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
- * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
- aarch64_field_kinds.
- (OPD_F_OD_MASK): Widen by one bit.
- (OPD_F_NO_ZR): Bump accordingly.
- (get_operand_field_width): New function.
- * aarch64-opc.c (fields): Add new SVE fields.
- (operand_general_constraint_met_p): Handle new SVE operands.
+ * aarch64-gen.c (print_operand_inserter): Use errors and change type to
+ boolean in aarch64_insert_operan.
+ (print_operand_extractor): Likewise.
+ * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
+
+2018-05-15 Francois H. Theron <francois.theron@netronome.com>
+
+ * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
+
+2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
+
+2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
+
+ * cr16-opc.c (cr16_instruction): Comment typo fix.
+ * hppa-dis.c (print_insn_hppa): Likewise.
+
+2018-05-08 Jim Wilson <jimw@sifive.com>
+
+ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
+ (match_c_slli64, match_srxi_as_c_srxi): New.
+ (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
+ <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
+ <c.slli, c.srli, c.srai>: Use match_s_slli.
+ <c.slli64, c.srli64, c.srai64>: New.
+
+2018-05-08 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
+ (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
+ partition opcode space for index lookup.
+
+2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
+ <insn_length>: ...with this. Update usage.
+ Remove duplicate call to *info->memory_error_func.
+
+2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (Gva): New.
+ (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
+ MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
+ (prefix_table): New instructions (see prefix above).
+ (mod_table): New instructions (see prefix above).
+ (OP_G): Handle va_mode.
+ * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
+ CPU_MOVDIR64B_FLAGS.
+ (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
+ * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
+ (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
+ * i386-opc.tbl: Add movidir{i,64b}.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
+ AddrPrefixOpReg.
+ * i386-opc.h (AddrPrefixOp0): Renamed to ...
+ (AddrPrefixOpReg): This.
+ (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
+ * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
+
+2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
+
+ * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
+ (vle_num_opcodes): Likewise.
+ (spe2_num_opcodes): Likewise.
+ * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
+ initialization loop.
+ (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
+ (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
+ only once.
+
+2018-05-01 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
+
+2018-04-30 Francois H. Theron <francois.theron@netronome.com>
+
+ Makefile.am: Added nfp-dis.c.
+ configure.ac: Added bfd_nfp_arch.
+ disassemble.h: Added print_insn_nfp prototype.
+ disassemble.c: Added ARCH_nfp and call to print_insn_nfp
+ nfp-dis.c: New, for NFP support.
+ po/POTFILES.in: Added nfp-dis.c to the list.
+ Makefile.in: Regenerate.
+ configure: Regenerate.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold various non-memory operand AVX512VL
+ templates into their base ones.
+ * i386-tlb.h: Re-generate.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
+ CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
+ CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
+ CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
+ * i386-init.h: Re-generate.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
+ CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
+ CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
+ Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
+ comment.
+ (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
+ and CpuRegMask.
+ * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
+ CpuRegMask: Delete.
+ (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
+ cpuregzmm, and cpuregmask.
+ * i386-init.h: Re-generate.
+ * i386-tbl.h: Re-generate.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
+ CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
+ * i386-init.h: Re-generate.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (VexImmExt): Delete.
+ * i386-opc.h (VexImmExt, veximmext): Delete.
+ * i386-opc.tbl: Drop all VexImmExt uses.
+ * i386-tlb.h: Re-generate.
+
+2018-04-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
+ register-only forms.
+ * i386-tlb.h: Re-generate.
+
+2018-04-25 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
+
+2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
+ PREFIX_0F1C.
+ * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
+ (cpu_flags): Add CpuCLDEMOTE.
+ * i386-init.h: Regenerate.
+ * i386-opc.h (enum): Add CpuCLDEMOTE,
+ (i386_cpu_flags): Add cpucldemote.
+ * i386-opc.tbl: Add cldemote.
+ * i386-tbl.h: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am: Remove sh5 and sh64 support.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * sh-dis.c: Likewise.
+ * sh64-dis.c: Delete.
+ * sh64-opc.c: Delete.
+ * sh64-opc.h: Delete.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am: Remove w65 support.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * w65-dis.c: Delete.
+ * w65-opc.h: Delete.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * configure.ac: Remove we32k support.
+ * configure: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am: Remove m88k support.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * m88k-dis.c: Delete.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am: Remove i370 support.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * i370-dis.c: Delete.
+ * i370-opc.c: Delete.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am: Remove h8500 support.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * h8500-dis.c: Delete.
+ * h8500-opc.h: Delete.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-04-16 Alan Modra <amodra@gmail.com>
+
+ * configure.ac: Remove tahoe support.
+ * configure: Regenerate.
+
+2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
+ umwait.
+ * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
+ 64-bit mode.
+ * i386-tbl.h: Regenerated.
+
+2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
+ PREFIX_MOD_1_0FAE_REG_6.
+ (va_mode): New.
+ (OP_E_register): Use va_mode.
+ * i386-dis-evex.h (prefix_table):
+ New instructions (see prefixes above).
+ * i386-gen.c (cpu_flag_init): Add WAITPKG.
+ (cpu_flags): Likewise.
+ * i386-opc.h (enum): Likewise.
+ (i386_cpu_flags): Likewise.
+ * i386-opc.tbl: Add umonitor, umwait, tpause.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2018-04-11 Alan Modra <amodra@gmail.com>
+
+ * opcodes/i860-dis.c: Delete.
+ * opcodes/i960-dis.c: Delete.
+ * Makefile.am: Remove i860 and i960 support.
+ * configure.ac: Likewise.
+ * disassemble.c: Likewise.
+ * disassemble.h: Likewise.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/23025
+ * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
+ to 0.
+ (print_insn): Clear vex instead of vex.evex.
+
+2018-04-04 Nick Clifton <nickc@redhat.com>
+
+ * po/es.po: Updated Spanish translation.
+
+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Delete VecESize.
+ * i386-opc.h (VecESize): Delete.
+ (struct i386_opcode_modifier): Delete vecesize.
+ * i386-opc.tbl: Drop VecESize.
+ * i386-tlb.h: Re-generate.
+
+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
+ BROADCAST_1TO4, BROADCAST_1TO2): Delete.
+ (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
+ * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
+ * i386-tlb.h: Re-generate.
+
+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
+ Fold AVX512 forms
+ * i386-tlb.h: Re-generate.
+
+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (prefix_table): Drop Y for cvt*2si.
+ (vex_len_table): Drop Y for vcvt*2si.
+ (putop): Replace plain 'Y' handling by abort().
+
+2018-03-28 Nick Clifton <nickc@redhat.com>
+
+ PR 22988
+ * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
+ instructions with only a base address register.
+ * aarch64-opc.c (operand_general_constraint_met_p): Add code to
+ handle AARHC64_OPND_SVE_ADDR_R.
(aarch64_print_operand): Likewise.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64_dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
-2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
+2018-03-22 Jan Beulich <jbeulich@suse.com>
- * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
- (aarch64_feature_compnum): ...this.
- (SIMD_V8_3): Replace with...
- (COMPNUM): ...this.
- (CNUM_INSN): New macro.
- (aarch64_opcode_table): Use it for the complex number instructions.
+ * i386-opc.tbl: Drop VecESize from register only insn forms and
+ memory forms not allowing broadcast.
+ * i386-tlb.h: Re-generate.
-2017-02-24 Jan Beulich <jbeulich@suse.com>
+2018-03-22 Jan Beulich <jbeulich@suse.com>
- * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
+ * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
+ vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
+ sha256*): Drop Disp<N>.
-2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
+2018-03-22 Jan Beulich <jbeulich@suse.com>
- Add support for associating SPARC ASIs with an architecture level.
- * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
- * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
- decoding of SPARC ASIs.
+ * i386-dis.c (EbndS, bnd_swap_mode): New.
+ (prefix_table): Use EbndS.
+ (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
+ * i386-opc.tbl (bndmov): Move misplaced Load.
+ * i386-tlb.h: Re-generate.
-2017-02-23 Jan Beulich <jbeulich@suse.com>
+2018-03-22 Jan Beulich <jbeulich@suse.com>
- * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
- 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
+ * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
+ templates allowing memory operands and folded ones for register
+ only flavors.
+ * i386-tlb.h: Re-generate.
-2017-02-21 Jan Beulich <jbeulich@suse.com>
+2018-03-22 Jan Beulich <jbeulich@suse.com>
- * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
- 1 (instead of to itself). Correct typo.
+ * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
+ 256-bit templates. Drop redundant leftover Disp<N>.
+ * i386-tlb.h: Re-generate.
-2017-02-14 Andrew Waterman <andrew@sifive.com>
+2018-03-14 Kito Cheng <kito.cheng@gmail.com>
- * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
- pseudoinstructions.
+ * riscv-opc.c (riscv_insn_types): New.
-2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
+2018-03-13 Nick Clifton <nickc@redhat.com>
- * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
- (aarch64_sys_reg_supported_p): Handle them.
+ * po/pt_BR.po: Updated Brazilian Portuguese translation.
-2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
+2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
- * arc-opc.c (UIMM6_20R): Define.
- (SIMM12_20): Use above.
- (SIMM12_20R): Define.
- (SIMM3_5_S): Use above.
- (UIMM7_A32_11R_S): Define.
- (UIMM7_9_S): Use above.
- (UIMM3_13R_S): Define.
- (SIMM11_A32_7_S): Use above.
- (SIMM9_8R): Define.
- (UIMM10_A32_8_S): Use above.
- (UIMM8_8R_S): Define.
- (W6): Use above.
- (arc_relax_opcodes): Use all above defines.
+ * i386-opc.tbl: Add Optimize to clr.
+ * i386-tbl.h: Regenerated.
-2017-02-15 Vineet Gupta <vgupta@synopsys.com>
+2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
- * arc-regs.h: Distinguish some of the registers different on
- ARC700 and HS38 cpus.
+ * i386-gen.c (opcode_modifiers): Remove OldGcc.
+ * i386-opc.h (OldGcc): Removed.
+ (i386_opcode_modifier): Remove oldgcc.
+ * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
+ instructions for old (<= 2.8.1) versions of gcc.
+ * i386-tbl.h: Regenerated.
-2017-02-14 Alan Modra <amodra@gmail.com>
+2018-03-08 Jan Beulich <jbeulich@suse.com>
- PR 21118
- * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
- with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
+ * i386-opc.h (EVEXDYN): New.
+ * i386-opc.tbl: Fold various AVX512VL templates.
+ * i386-tlb.h: Re-generate.
-2017-02-11 Stafford Horne <shorne@gmail.com>
- Alan Modra <amodra@gmail.com>
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
+ vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
+ vpexpandd, vpexpandq): Fold AFX512VF templates.
+ * i386-tlb.h: Re-generate.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
+ Fold 128- and 256-bit VEX-encoded templates.
+ * i386-tlb.h: Re-generate.
- * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
- Use insn_bytes_value and insn_int_value directly instead. Don't
- free allocated memory until function exit.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-02-10 Nicholas Piggin <npiggin@gmail.com>
+ * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
+ vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
+ vpexpandd, vpexpandq): Fold AVX512F templates.
+ * i386-tlb.h: Re-generate.
- * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-02-03 Nick Clifton <nickc@redhat.com>
+ * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
+ 64-bit templates. Drop Disp<N>.
+ * i386-tlb.h: Re-generate.
- PR 21096
- * aarch64-opc.c (print_register_list): Ensure that the register
- list index will fir into the tb buffer.
- (print_register_offset_address): Likewise.
- * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
+ * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
+ and 256-bit templates.
+ * i386-tlb.h: Re-generate.
- PR 21056
- * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
- instructions when the previous fetch packet ends with a 32-bit
- instruction.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
+ * i386-opc.tbl (cmpxchg8b): Add NoRex64.
+ * i386-tlb.h: Re-generate.
- * pru-opc.c: Remove vague reference to a future GDB port.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-20 Nick Clifton <nickc@redhat.com>
+ * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
+ Drop NoAVX.
+ * i386-tlb.h: Re-generate.
- * po/ga.po: Updated Irish translation.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+ * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
+ * i386-tlb.h: Re-generate.
- * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-13 Yao Qi <yao.qi@linaro.org>
+ * i386-gen.c (opcode_modifiers): Delete FloatD.
+ * i386-opc.h (FloatD): Delete.
+ (struct i386_opcode_modifier): Delete floatd.
+ * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
+ FloatD by D.
+ * i386-tlb.h: Re-generate.
- * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
- if FETCH_DATA returns 0.
- (m68k_scan_mask): Likewise.
- (print_insn_m68k): Update code to handle -1 return value.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-13 Yao Qi <yao.qi@linaro.org>
+ * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
- * m68k-dis.c (enum print_insn_arg_error): New.
- (NEXTBYTE): Replace -3 with
- PRINT_INSN_ARG_MEMORY_ERROR.
- (NEXTULONG): Likewise.
- (NEXTSINGLE): Likewise.
- (NEXTDOUBLE): Likewise.
- (NEXTDOUBLE): Likewise.
- (NEXTPACKED): Likewise.
- (FETCH_ARG): Likewise.
- (FETCH_DATA): Update comments.
- (print_insn_arg): Update comments. Replace magic numbers with
- enum.
- (match_insn_m68k): Likewise.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
-2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ * i386-opc.tbl (vmovd): Disallow Qword memory operands.
+ * i386-tlb.h: Re-generate.
- * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
- * i386-dis-evex.h (evex_table): Updated.
- * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
- CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
- (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
- * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
- (i386_cpu_flags): Add cpuavx512_vpopcntdq.
- * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
+ forms.
+ * i386-tlb.h: Re-generate.
+
+2018-03-07 Alan Modra <amodra@gmail.com>
+
+ * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
+ bfd_arch_rs6000.
+ * disassemble.h (print_insn_rs6000): Delete.
+ * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
+ (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
+ (print_insn_rs6000): Delete.
+
+2018-03-03 Alan Modra <amodra@gmail.com>
+
+ * sysdep.h (opcodes_error_handler): Define.
+ (_bfd_error_handler): Declare.
+ * Makefile.am: Remove stray #.
+ * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
+ EDIT" comment.
+ * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
+ * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
+ * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
+ opcodes_error_handler to print errors. Standardize error messages.
+ * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
+ and include opintl.h.
+ * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
+ * i386-gen.c: Standardize error messages.
+ * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
+ * Makefile.in: Regenerate.
+ * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
+ * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
+ * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
+ * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
+ * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
+ * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
+ * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
+ * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
+ * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
+ * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
+ * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
+ * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
+ * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
+
+2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
+ vpsub[bwdq] instructions.
+ * i386-tbl.h: Regenerated.
+
+2018-03-01 Alan Modra <amodra@gmail.com>
+
+ * configure.ac (ALL_LINGUAS): Sort.
+ * configure: Regenerate.
+
+2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
+ macro by assignements.
+
+2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/22871
+ * i386-gen.c (opcode_modifiers): Add Optimize.
+ * i386-opc.h (Optimize): New enum.
+ (i386_opcode_modifier): Add optimize.
+ * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
+ "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
+ "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
+ "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
+ vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
+ vpxord and vpxorq.
+ * i386-tbl.h: Regenerated.
+
+2018-02-26 Alan Modra <amodra@gmail.com>
+
+ * crx-dis.c (getregliststring): Allocate a large enough buffer
+ to silence false positive gcc8 warning.
+
+2018-02-22 Shea Levy <shea@shealevy.com>
+
+ * disassemble.c (ARCH_riscv): Define if ARCH_all.
+
+2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add {rex},
+ * i386-tbl.h: Regenerated.
+
+2018-02-20 Maciej W. Rozycki <macro@mips.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
+ (mips16_opcodes): Replace `M' with `m' for "restore".
+
+2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (thumb_opcodes): Fix BXNS mask.
+
+2018-02-13 Maciej W. Rozycki <macro@mips.com>
+
+ * wasm32-dis.c (print_insn_wasm32): Rename `index' local
+ variable to `function_index'.
+
+2018-02-13 Nick Clifton <nickc@redhat.com>
+
+ PR 22823
+ * metag-dis.c (print_fmmov): Double buffer size to avoid warning
+ about truncation of printing.
+
+2018-02-12 Henry Wong <henry@stuffedcow.net>
+
+ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
+
+2018-02-05 Nick Clifton <nickc@redhat.com>
+
+ * po/pt_BR.po: Updated Brazilian Portuguese translation.
+
+2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add pconfig.
+ * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
+ (cpu_flags): Add CpuPCONFIG.
+ * i386-opc.h (enum): Add CpuPCONFIG.
+ (i386_cpu_flags): Add cpupconfig.
+ * i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
- * i386-tbl.h: Ditto.
+ * i386-tbl.h: Likewise.
+
+2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F09.
+ * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
+ (cpu_flags): Add CpuWBNOINVD.
+ * i386-opc.h (enum): Add CpuWBNOINVD.
+ (i386_cpu_flags): Add cpuwbnoinvd.
+ * i386-opc.tbl: Add WBNOINVD instruction.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
-2017-01-12 Yao Qi <yao.qi@linaro.org>
+2018-01-17 Jim Wilson <jimw@sifive.com>
- * msp430-dis.c (msp430_singleoperand): Return -1 if
- msp430dis_opcode_signed returns false.
- (msp430_doubleoperand): Likewise.
- (msp430_branchinstr): Return -1 if
- msp430dis_opcode_unsigned returns false.
- (msp430x_calla_instr): Likewise.
- (print_insn_msp430): Likewise.
+ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
+
+2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
+ Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
+ CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
+ (cpu_flags): Add CpuIBT, CpuSHSTK.
+ * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
+ (i386_cpu_flags): Add cpuibt, cpushstk.
+ * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
-2017-01-05 Nick Clifton <nickc@redhat.com>
+2018-01-16 Nick Clifton <nickc@redhat.com>
- PR 20946
- * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
- could not be matched.
- (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
- NULL.
+ * po/pt_BR.po: Updated Brazilian Portugese translation.
+ * po/de.po: Updated German translation.
-2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
+2018-01-15 Jim Wilson <jimw@sifive.com>
- * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
- (aarch64_opcode_table): Use RCPC_INSN.
+ * riscv-opc.c (match_c_nop): New.
+ (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
-2017-01-03 Kito Cheng <kito.cheng@gmail.com>
+2018-01-15 Nick Clifton <nickc@redhat.com>
- * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
- extension.
- * riscv-opcodes/all-opcodes: Likewise.
+ * po/uk.po: Updated Ukranian translation.
-2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
+2018-01-13 Nick Clifton <nickc@redhat.com>
- * riscv-dis.c (print_insn_args): Add fall through comment.
+ * po/opcodes.pot: Regenerated.
-2017-01-03 Nick Clifton <nickc@redhat.com>
+2018-01-13 Nick Clifton <nickc@redhat.com>
- * po/sr.po: New Serbian translation.
- * configure.ac (ALL_LINGUAS): Add sr.
* configure: Regenerate.
-2017-01-02 Alan Modra <amodra@gmail.com>
-
- * epiphany-desc.h: Regenerate.
- * epiphany-opc.h: Regenerate.
- * fr30-desc.h: Regenerate.
- * fr30-opc.h: Regenerate.
- * frv-desc.h: Regenerate.
- * frv-opc.h: Regenerate.
- * ip2k-desc.h: Regenerate.
- * ip2k-opc.h: Regenerate.
- * iq2000-desc.h: Regenerate.
- * iq2000-opc.h: Regenerate.
- * lm32-desc.h: Regenerate.
- * lm32-opc.h: Regenerate.
- * m32c-desc.h: Regenerate.
- * m32c-opc.h: Regenerate.
- * m32r-desc.h: Regenerate.
- * m32r-opc.h: Regenerate.
- * mep-desc.h: Regenerate.
- * mep-opc.h: Regenerate.
- * mt-desc.h: Regenerate.
- * mt-opc.h: Regenerate.
- * or1k-desc.h: Regenerate.
- * or1k-opc.h: Regenerate.
- * xc16x-desc.h: Regenerate.
- * xc16x-opc.h: Regenerate.
- * xstormy16-desc.h: Regenerate.
- * xstormy16-opc.h: Regenerate.
+2018-01-13 Nick Clifton <nickc@redhat.com>
+
+ 2.30 branch created.
+
+2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
+ * i386-tbl.h: Regenerate.
+
+2018-01-10 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
+ * i386-tbl.h: Re-generate.
+
+2018-01-10 Jan Beulich <jbeulich@suse.com>
-2017-01-02 Alan Modra <amodra@gmail.com>
+ * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
+ vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
+ vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
+ vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
+ vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
+ Disp8MemShift of AVX512VL forms.
+ * i386-tbl.h: Re-generate.
+
+2018-01-09 Jim Wilson <jimw@sifive.com>
+
+ * riscv-dis.c (maybe_print_address): If base_reg is zero,
+ then the hi_addr value is zero.
+
+2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add csdb.
+ (thumb32_opcodes): Add csdb.
+
+2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/22681
+ * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
+ Remove AVX512 vmovd with 64-bit operands.
+ * i386-tbl.h: Regenerated.
+
+2018-01-05 Jim Wilson <jimw@sifive.com>
+
+ * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
+ jalr.
+
+2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2016
+2018-01-02 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
+ and OPERAND_TYPE_REGZMM entries.
+
+For older changes see ChangeLog-2017
\f
-Copyright (C) 2017 Free Software Foundation, Inc.
+Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / deliverable / binutils-gdb.git / blobdiff