+2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
+ Stephane Carrez <stcarrez@nerim.fr>
+
+ * configure.in: Add S12X and XGATE co-processor support to m68hc11
+ target.
+ * disassemble.c: Likewise.
+ * configure: Regenerate.
+ * m68hc11-dis.c: Make objdump output more consistent, use hex
+ instead of decimal and use 0x prefix for hex.
+ * m68hc11-opc.c: Add S12X and XGATE opcodes.
+
+2012-05-14 James Lemke <jwlemke@codesourcery.com>
+
+ * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
+ (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
+ (vle_opcd_indices): New array.
+ (lookup_vle): New function.
+ (disassemble_init_powerpc): Revise for second (VLE) opcode table.
+ (print_insn_powerpc): Likewise.
+ * ppc-opc.c: Likewise.
+
+2012-05-14 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Rhonda Wittels <rhonda@codesourcery.com>
+ Nathan Froyd <froydnj@codesourcery.com>
+
+ * ppc-opc.c (insert_arx, extract_arx): New functions.
+ (insert_ary, extract_ary): New functions.
+ (insert_li20, extract_li20): New functions.
+ (insert_rx, extract_rx): New functions.
+ (insert_ry, extract_ry): New functions.
+ (insert_sci8, extract_sci8): New functions.
+ (insert_sci8n, extract_sci8n): New functions.
+ (insert_sd4h, extract_sd4h): New functions.
+ (insert_sd4w, extract_sd4w): New functions.
+ (insert_vlesi, extract_vlesi): New functions.
+ (insert_vlensi, extract_vlensi): New functions.
+ (insert_vleui, extract_vleui): New functions.
+ (insert_vleil, extract_vleil): New functions.
+ (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
+ (BI16, BI32, BO32, B8): New.
+ (B15, B24, CRD32, CRS): New.
+ (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
+ (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
+ (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
+ (SH6_MASK): Use PPC_OPSHIFT_INV.
+ (SI8, UI5, OIMM5, UI7, BO16): New.
+ (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
+ (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
+ (ALLOW8_SPRG): New.
+ (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
+ (OPVUP, OPVUP_MASK OPVUP): New
+ (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
+ (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
+ (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
+ (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
+ (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
+ (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
+ (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
+ (SE_IM5, SE_IM5_MASK): New.
+ (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
+ (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
+ (BO32DNZ, BO32DZ): New.
+ (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
+ (PPCVLE): New.
+ (powerpc_opcodes): Add new VLE instructions. Update existing
+ instruction to include PPCVLE if supported.
+ * ppc-dis.c (ppc_opts): Add vle entry.
+ (get_powerpc_dialect): New function.
+ (powerpc_init_dialect): VLE support.
+ (print_insn_big_powerpc): Call get_powerpc_dialect.
+ (print_insn_little_powerpc): Likewise.
+ (operand_value_powerpc): Handle negative shift counts.
+ (print_insn_powerpc): Handle 2-byte instruction lengths.
+
+2012-05-11 Daniel Richard G. <skunk@iskunk.org>
+
+ PR binutils/14028
+ * configure.in: Invoke ACX_HEADER_STRING.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * sysdep.h: If STRINGS_WITH_STRING is defined then include both
+ string.h and strings.h.
+
+2012-05-11 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/14006
+ * arm-dis.c (print_insn): Fix detection of instruction mode in
+ files containing multiple executable sections.
+
+2012-05-03 Sean Keys <skeys@ipdatasys.com>
+
+ * Makefile.in, configure: regenerate
+ * disassemble.c (disassembler): Recognize ARCH_XGATE.
+ * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
+ New functions.
+ * configure.in: Recognize xgate.
+ * xgate-dis.c, xgate-opc.c: New files for support of xgate
+ * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
+ and opcode generation for xgate.
+
+2012-04-30 DJ Delorie <dj@redhat.com>
+
+ * rx-decode.opc (MOV): Do not sign-extend immediates which are
+ already the maximum bit size.
+ * rx-decode.c: Regenerate.
+
+2012-04-27 David S. Miller <davem@davemloft.net>
+
+ * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
+ * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
+
+ * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
+ * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
+
+ * sparc-opc.c (CBCOND): New define.
+ (CBCOND_XCC): Likewise.
+ (cbcond): New helper macro.
+ (sparc_opcodes): Add compare-and-branch instructions.
+
+ * sparc-dis.c (print_insn_sparc): Handle ')'.
+ * sparc-opc.c (sparc_opcodes): Add crypto instructions.
+
+ * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
+ into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
+
+2012-04-12 David S. Miller <davem@davemloft.net>
+
+ * sparc-dis.c (X_DISP10): Define.
+ (print_insn_sparc): Handle '='.
+
+2012-04-01 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin-dis.c (fmtconst): Replace decimal handling with a single
+ sprintf call and the '*' field width.
+
+2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
+
+ * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
+
+2012-03-16 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
+ (powerpc_opcd_indices): Bump array size.
+ (disassemble_init_powerpc): Set powerpc_opcd_indices entries
+ corresponding to unused opcodes to following entry.
+ (lookup_powerpc): New function, extracted and optimised from..
+ (print_insn_powerpc): ..here.
+
+2012-03-15 Alan Modra <amodra@gmail.com>
+ James Lemke <jwlemke@codesourcery.com>
+
+ * disassemble.c (disassemble_init_for_target): Handle ppc init.
+ * ppc-dis.c (private): New var.
+ (powerpc_init_dialect): Don't return calloc failure, instead use
+ private.
+ (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
+ (powerpc_opcd_indices): New array.
+ (disassemble_init_powerpc): New function.
+ (print_insn_big_powerpc): Don't init dialect here.
+ (print_insn_little_powerpc): Likewise.
+ (print_insn_powerpc): Start search using powerpc_opcd_indices.
+
+2012-03-10 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
+ * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
+ (PPCVEC2, PPCTMR, E6500): New short names.
+ (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
+ mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
+ lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
+ lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
+ lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
+ optional operands on sync instruction for E6500 target.
+
+2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
+
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * mt-dis.c: Regenerate.
+
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * v850-opc.c (extract_v8): Rearrange to make it obvious this
+ is the inverse of corresponding insert function.
+ (extract_d22, extract_u9, extract_r4): Likewise.
+ (extract_d9): Correct sign extension.
+ (extract_d16_15): Don't assume "long" is 32 bits, and don't
+ rely on implementation defined behaviour for shift right of
+ signed types.
+ (extract_d16_16, extract_d17_16, extract_i9): Likewise.
+ (extract_d23): Likewise, and correct mask.
+
+2012-02-27 Alan Modra <amodra@gmail.com>
+
+ * crx-dis.c (print_arg): Mask constant to 32 bits.
+ * crx-opc.c (cst4_map): Use int array.
+
2012-02-27 Alan Modra <amodra@gmail.com>
* arc-dis.c (BITS): Don't use shifts to mask off bits.
projects / deliverable / binutils-gdb.git / blobdiff