+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
+ (extractps): Add VexWIG to SSE2AVX forms.
+ * i386-tbl.h: Re-generate.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
+ Size64 from and use VexW1 on SSE2AVX forms.
+ (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
+ VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
+ * i386-tbl.h: Re-generate.
+
+2020-01-15 Alan Modra <amodra@gmail.com>
+
+ * tic4x-dis.c (tic4x_version): Make unsigned long.
+ (optab, optab_special, registernames): New file scope vars.
+ (tic4x_print_register): Set up registernames rather than
+ malloc'd registertable.
+ (tic4x_disassemble): Delete optable and optable_special. Use
+ optab and optab_special instead. Throw away old optab,
+ optab_special and registernames when info->mach changes.
+
+2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25377
+ * z80-dis.c (suffix): Use .db instruction to generate double
+ prefix.
+
+2020-01-14 Alan Modra <amodra@gmail.com>
+
+ * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
+ values to unsigned before shifting.
+
+2020-01-13 Thomas Troeger <tstroege@gmx.de>
+
+ * arm-dis.c (print_insn_arm): Fill in insn info fields for control
+ flow instructions.
+ (print_insn_thumb16, print_insn_thumb32): Likewise.
+ (print_insn): Initialize the insn info.
+ * i386-dis.c (print_insn): Initialize the insn info fields, and
+ detect jumps.
+
2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
* arc-opc.c (C_NE): Make it required.