* mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6f7043fb3868e0d4494b8201b3f25401a9afd82a..b3e2cec71db8aaaa88a69ee62599243e462012f2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,42 @@
+2000-05-21  Nick Clifton  <nickc@cygnus.com>
+
+       * Makefile.am (LIBIBERTY): Define.
+
+Fri May 19 12:29:27 EDT 2000   Diego Novillo <dnovillo@redhat.com>
+
+       * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
+       (STD_REGISTER_NAMES): New name for REGISTER_NAMES.
+       (reg_names): Rename to std_reg_names. Change it to a char **
+       static variable.
+       (std_reg_names): New name for reg_names.
+       (set_mips_isa_type): Set reg_names to point to std_reg_names by
+       default.
+
+2000-05-16  Frank Ch. Eigler  <fche@redhat.com>
+
+       * fr30-desc.h: Partially regenerated to account for changed
+       CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
+       * m32r-desc.h: Ditto.
+
+2000-05-15  Nick Clifton  <nickc@cygnus.com>
+
+       * arm-opc.h: Use upper case for flasg in MSR and MRS
+       instructions.  Allow any bit to be set in the field_mask of
+       the MSR instruction.
+
+       * arm-dis.c (print_insn_arm): Decode _x and _s bits of the
+       field_mask of an MSR instruction.
+
+2000-05-11  Thomas de Lellis  <tdel@windriver.com>
+
+        * arm-opc.c: Disassembly of thumb ldsb/ldsh
+        instructions changed to ldrsb/ldrsh.
+       
+2000-05-11  Ulf Carlsson  <ulfc@engr.sgi.com>
+
+       * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
+       target addresses for 'jal' and 'j'.
+
 2000-05-10  Geoff Keating  <geoffk@cygnus.com>
 
        * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes