RISC-V: Report warning when linking the objects with different priv specs.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
index 6b3869f0f01569a310745619d9c8143ed8a9b9ca..ba0febec558108a3dc46f6d71c4a58a0642644ae 100644 (file)
@@ -1,3 +1,54 @@
+2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
+       * riscv-dis.c: Include elfxx-riscv.h.
+
+2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (prefix_table): Revert the last vmgexit change.
+
+2020-06-17  Lili Cui  <lili.cui@intel.com>
+
+       * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
+
+2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/26115
+       * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
+       * i386-opc.tbl: Likewise.
+       * i386-tbl.h: Regenerated.
+
+2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
+
+2020-06-11  Alex Coplan  <alex.coplan@arm.com>
+
+       * aarch64-opc.c (SYSREG): New macro for describing system registers.
+       (SR_CORE): Likewise.
+       (SR_FEAT): Likewise.
+       (SR_RNG): Likewise.
+       (SR_V8_1): Likewise.
+       (SR_V8_2): Likewise.
+       (SR_V8_3): Likewise.
+       (SR_V8_4): Likewise.
+       (SR_PAN): Likewise.
+       (SR_RAS): Likewise.
+       (SR_SSBS): Likewise.
+       (SR_SVE): Likewise.
+       (SR_ID_PFR2): Likewise.
+       (SR_PROFILE): Likewise.
+       (SR_MEMTAG): Likewise.
+       (SR_SCXTNUM): Likewise.
+       (aarch64_sys_regs): Refactor to store feature information in the table.
+       (aarch64_sys_reg_supported_p): Collapse logic for system registers
+       that now describe their own features.
+       (aarch64_pstatefield_supported_p): Likewise.
+
+2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (prefix_table): Fix a typo in comments.
+
 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 
        * i386-dis.c (rex_ignored): Delete.
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