Fix MTSA opcode encoding.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f2196bac3cc7dc36bfe4ac002b7de7bd8e1d9da4..c03034f226cd5c65daa7caa54b006da5c6544f14 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,84 @@
+start-sanitize-r5900
+Mon Jul 28 22:07:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * mips-opc.c: Fix coding of mtsa.
+
+start-sanitize-r5900
+Thu Jul 24 13:03:26 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+       * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns.
+       Make array const.
+       * sparc-dis.c (sorted_opcodes): New static local.
+       (struct opcode_hash): `opcode' is pointer to const element.
+       (build_hash): First arg is now table of sorted pointers.
+       (print_insn_sparc): Sort opcodes by sorting table of pointers.
+       (compare_opcodes): Update.
+
+Tue Jul 15 12:05:23 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+       * cgen-opc.c: #include <ctype.h>.
+       (hash_keyword_name): New arg `case_sensitive_p'.  Callers updated.
+       Handle case insensitive hashing.
+       (hash_keyword_value): Change type of `value' to unsigned int.
+
+Thu Jul 10 12:56:10 1997  Jeffrey A Law  (law@cygnus.com)
+
+       * mips-opc.c (mips_builtin_opcodes): If an insn uses single
+       precision FP, mark it as such.  Likewise for double precision
+       FP.  Mark ISA1 insns.  Consolidate duplicate opcodes where
+       possible.
+start-sanitize-r5900
+       (mips_builtin_opcodes): Remove non-existant r5900 instructions
+end-sanitize-r5900
+
+start-sanitize-r5900
+Thu Jun 26 16:20:27 1997  Jeffrey A Law  (law@cygnus.com)
+
+       * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and
+       "pexew" as synonyms for "pintoh", "pexoh", "pexow".
+
+end-sanitize-5900
+Wed Jun 25 15:25:57 1997  Felix Lee  <flee@cirdan.cygnus.com>
+
+       * ppc-opc.c (extract_nsi): make unsigned expression signed before
+       negating it.
+       (UNUSED): remove one level of parens, so MSVC doesn't choke on
+       nesting depth when all the macros are expanded.
+       
+Tue Jun 17 17:02:17 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+       * sparc-opc.c: The fcmp v9a instructions take an integer register
+       as a destination, not a floating point register.  From Christian
+       Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>.
+
+Mon Jun 16 14:13:18 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+       * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@()
+       syntax.  From Roman Hodek
+       <rnhodek@faui22c.informatik.uni-erlangen.de>.
+
+       * i386-dis.c (twobyte_has_modrm): Fix pand.
+
+Mon Jun 16 14:08:38 1997  Michael Taylor  <mbt@mit.edu>
+
+       * i386-dis.c (dis386_twobyte): Fix pand and pandn.
+
+Tue Jun 10 11:26:47 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+       * arm-dis.c: Add prototypes for arm_decode_shift and
+       print_insn_arm.
+
+Mon Jun  2 11:39:04 1997  Gavin Koch  <gavin@cygnus.com>
+
+       * mips-opc.c: Add r3900 insns.
+
+Tue May 27 15:55:44 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+       * sh-dis.c (print_insn_shx): Change relmask to bfd_vma.  Don't
+       print delay slot instructions on the same line.  When using a PC
+       relative load, add a comment with the value being loaded if it can
+       be obtained.
+
 Tue May 27 11:02:08 1997  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
        * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl