* v850-opc.c (v850_operands): Define SR2 operand.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4da63185fae95dcd1574aa6509dd5a738ffc1d3c..c4ecb12dd123702435ef340a1b7429e199560bf7 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,7 +1,57 @@
 start-sanitize-v850
+Thu Aug 29 11:10:46 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * v850-opc.c (v850_operands): Define SR2 operand.
+       (v850_opcodes): "ldsr" uses R1,SR2.
+
+       * v850-opc.c (v850_opcodes): Fix opcode specs for
+       sld.w, sst.b, sst.h, sst.w, and nop.
+
+Wed Aug 28 15:55:43 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * v850-opc.c (v850_opcodes): Add null opcode to mark the
+       end of the opcode table.
+
+end-sanitize-v850
+start-sanitize-d10v
+Mon Aug 26 13:35:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+       * d10v-opc.c (pre_defined_registers): Added register pairs,
+       "r0-r1", "r2-r3", etc.
+
+end-sanitize-d10v      
+start-sanitize-v850
 Fri Aug 23 00:27:01 1996  Jeffrey A Law  (law@cygnus.com)
 
-       * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.
+       * v850-opc.c (v850_operands): Make I16 be a signed operand.
+       Create I16U for an unsigned 16bit mmediate operand.
+       (v850_opcodes): Use I16U for "ori", "andi" and "xori".
+
+       * v850-opc.c (v850_operands): Define EP operand.
+       (IF4A, IF4B, IF4C, IF4D): Use EP.
+
+       * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"
+       with immediate operand, "movhi".  Tweak "ldsr".
+
+       * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]
+       correct.  Get sld.[bhw] and sst.[bhw] closer.
+
+       * v850-opc.c (v850_operands): "not" is a two byte insn
+
+       * v850-opc.c (v850_opcodes): Correct bit pattern for setf.
+
+       * v850-opc.c (v850_operands): D16 inserts at offset 16!
+
+       * v850-opc.c (two): Get order of words correct.
+
+       * v850-opc.c (v850_operands): I16 inserts at offset 16!
+
+       * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system
+       register source and destination operands.
+       (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
+
+       * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.  Fix
+       same thinko in "trap" opcode.
 
        * v850-opc.c (v850_opcodes): Add initializer for size field
        on all opcodes.