+2000-11-14 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris-dis.c (cris_get_disassembler): If abfd is NULL, return
+ print_insn_cris_with_register_prefix.
+
+2000-11-11 Alexandre Oliva <aoliva@redhat.com>
+
+ * sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0.
+
+2000-11-07 Matthew Green <mrg@redhat.com>
+
+ * cgen-dis.in (print_insn): All insns which can fit into insn_value
+ must be loaded there in their entirety.
+
+2000-10-20 Jakub Jelinek <jakub@redhat.com>
+
+ * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
+ (compute_arch_mask): Add v8plusb and v9b machines.
+ (print_insn_sparc): siam mode decoding, accept ASRs up to 25.
+ * opcodes/sparc-opc.c: Support for Cheetah instruction set.
+ (prefetch_table): Add #invalidate.
+
+2000-10-16 Nick Clifton <nickc@redhat.com>
+
+ * mcore-dis.c (imsk): Change mask for OC to 0xFE00.
+
+2000-10-06 Dave Brolley <brolley@redhat.com>
+
+ * fr30-desc.h: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * m32r-ibld.c: Regenerate.
+
+2000-10-05 Jim Wilson <wilson@cygnus.com>
+
+ * ia64-ic.tbl: Update from Intel.
+ * ia64-asmtab.c: Regenerate.
+
+2000-10-04 Kazu Hirata <kazu@hxi.com>
+
+ * ia64-gen.c: Convert C++-style comments to C-style comments.
+ * tic54x-dis.c: Likewise.
+
+2000-09-29 Hans-Peter Nilsson <hp@axis.com>
+
+ Changes to add dollar prefix to registers for files where user symbols
+ don't have a leading underscore. Fix formatting.
+ * cris-dis.c (REGISTER_PREFIX_CHAR): New.
+ (format_reg): Add parameter with_reg_prefix. All callers changed.
+ (print_with_operands): Ditto.
+ (print_insn_cris_generic): Renamed from print_insn_cris, add
+ parameter with_reg_prefix.
+ (print_insn_cris_with_register_prefix,
+ print_insn_cris_without_register_prefix, cris_get_disassembler):
+ New.
+ * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
+
+2000-09-22 Jim Wilson <wilson@cygnus.com>
+
+ * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
+ gt, ge, ngt, and nge.
+ * ia64-asmtab.c: Regenerate.
+
+ * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
+ * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
+ (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
+ * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
+ * ia64-asmtab.c: Regnerate.
+
+2000-09-13 Anders Norlander <anorland@acc.umu.se>
+
+ * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
+ Add mfc0 and mtc0 with sub-selection values.
+ Add clo and clz opcodes.
+ Add msub and msubu instructions for MIPS32.
+ Add madd/maddu aliases for mad/madu for MIPS32.
+ Support wait, deret, eret, movn, pref for MIPS32.
+ Support tlbp, tlbr, tlbwi, tlbwr.
+ (P4): New define.
+
+ * mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
+ (print_insn_arg): Handle 'H' args.
+ (set_mips_isa_type): Recognize 4K.
+ Use CPU_* defines instead of hardcoded numbers.
+
+2000-09-11 Catherine Moore <clm@redhat.com>
+
+ * d30v-opc.c (d30v_operand_t): New operand type Rb2.
+ (d30v_format_tab): Use Rb2 for modinc and moddec.
+
+2000-09-07 Catherine Moore <clm@redhat.com>
+
+ * d30v-opc.c (d30v_format_tab): Use format Ra for
+ modinc and moddec.
+
+2000-09-06 Alexandre Oliva <aoliva@redhat.com>
+
+ * configure: Rebuilt with new libtool.m4.
+
+2000-09-05 Nick Clifton <nickc@redhat.com>
+
+ * configure: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
+2000-08-31 Alexandre Oliva <aoliva@redhat.com>
+
+ * acinclude.m4: Include libtool and gettext macros from the
+ top level.
+ * aclocal.m4, configure: Rebuilt.
+
+2000-08-30 Kazu Hirata <kazu@hxi.com>
+
+ * tic80-dis.c: Fix formatting.
+
+2000-08-29 Kazu Hirata <kazu@hxi.com>
+
+ * w65-dis.c: Fix formatting.
+
+2000-08-28 Mark Hatle <mhatle@mvista.com>
+
+ * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics.
+ (powerpc_opcodes): Add table entries for PPC 405 instructions.
+ Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
+ instructions. Added extended mnemonic mftbl as defined in the
+ 405GP manual for all PPCs.
+
+2000-08-28 Jim Wilson <wilson@cygnus.com>
+
+ * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
+ call. Change last goto to use failed instead of done.
+
+2000-08-28 Dave Brolley <brolley@redhat.com>
+
+ * cgen-ibld.in (cgen_put_insn_int_value): New function.
+ (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
+ (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
+ (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
+ * cgen-dis.in (read_insn): New static function.
+ (print_insn): Use read_insn to read the insn into the buffer and set
+ up for disassembly.
+ (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
+ in the buffer.
+ * fr30-asm.c: Regenerated.
+ * fr30-desc.c: Regenerated.
+ * fr30-desc.h Regenerated.
+ * fr30-dis.c: Regenerated.
+ * fr30-ibld.c: Regenerated.
+ * fr30-opc.c: Regenerated.
+ * fr30-opc.h Regenerated.
+ * m32r-asm.c: Regenerated.
+ * m32r-desc.c: Regenerated.
+ * m32r-desc.h Regenerated.
+ * m32r-dis.c: Regenerated.
+ * m32r-ibld.c: Regenerated.
+ * m32r-opc.c: Regenerated.
+
+2000-08-28 Kazu Hirata <kazu@hxi.com>
+
+ * tic30-dis.c: Fix formatting.
+
+2000-08-27 Kazu Hirata <kazu@hxi.com>
+
+ * sh-dis.c: Fix formatting.
+
+2000-08-24 David Edelsohn <dje@watson.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
+
+2000-08-24 Kazu Hirata <kazu@hxi.com>
+
+ * z8k-dis.c: Fix formatting.
+
+2000-08-16 Jim Wilson <wilson@cygnus.com>
+
+ * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
+ break, mov-immediate, nop.
+ * ia64-opc-f.c: Delete fpsub instructions.
+ * ia64-opc-m.c: Add POSTINC to all instructions with postincrement
+ address operand. Rewrite using macros to avoid long lines.
+ * ia64-opc.h (POSTINC): Define.
+ * ia64-asmtab.c: Regenerate.
+
+2000-08-15 Jim Wilson <wilson@cygnus.com>
+
+ * ia64-ic.tbl: Add missing entries.
+
+2000-08-08 Jason Eckhardt <jle@cygnus.com>
+
+ * i860-dis.c (print_br_address): Change third argument from int
+ to long.
+
+2000-08-07 Richard Henderson <rth@cygnus.com>
+
+ * ia64-dis.c (print_insn_ia64): Get byte skip count correct
+ for MLI templates. Handle IA64_OPND_TGT64.
+
+2000-08-04 Ben Elliston <bje@redhat.com>
+
+ * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
+ * cgen.sh: Likewise.
+
+2000-08-02 Jim Wilson <wilson@cygnus.com>
+
+ * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
+
+2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl>
+
+ * avr-dis.c (avr_operand): Use PARAMS macro in declaration.
+ Change return type from void to int. Check the combination
+ of operands, return 1 if valid. Fix to avoid BUF overflow.
+ Report undefined combinations of operands in COMMENT.
+ Report internal errors to stderr. Output the adiw/sbiw
+ constant operand in both decimal and hex.
+ (print_insn_avr): Disassemble ldd/std with displacement of 0
+ as ld/st. Check avr_operand () return value, handle invalid
+ combinations of operands like unknown opcodes.
+
+2000-07-28 Ben Elliston <bje@redhat.com>
+
+ * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New.
+ (run-cgen, stamp-m32r, stamp-fr30): New targets.
+ * Makefile.in: Regenerate.
+ * configure.in: Add --enable-cgen-maint option.
+ * configure: Regenerate.
+
+2000-07-26 Dave Brolley <brolley@redhat.com>
+
+ * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned.
+ (cgen_hw_lookup_by_num): Ditto.
+ (cgen_operand_lookup_by_name): Ditto.
+ (print_address): Ditto.
+ (print_keyword): Ditto.
+ * cgen-dis.c (hash_insn_array): Mark unused parameters with
+ ATTRIBUTE_UNUSED.
+ * cgen-asm.c (hash_insn_array): Mark unused parameters with
+ ATTRIBUTE_UNUSED.
+ (cgen_parse_keyword): Ditto.
+
+2000-07-22 Jason Eckhardt <jle@cygnus.com>
+
+ * i860-dis.c: New file.
+ (print_insn_i860): New function.
+ (print_br_address): New function.
+ (sign_extend): New function.
+ (BITWISE_OP): New macro.
+ (I860_REG_PREFIX): New macro.
+ (grnames, frnames, crnames): New structures.
+
+ * disassemble.c (ARCH_i860): Define.
+ (disassembler): Add check for bfd_arch_i860 to set disassemble
+ function to print_insn_i860.
+
+ * Makefile.in (CFILES): Added i860-dis.c.
+ (ALL_MACHINES): Added i860-dis.lo.
+ (i860-dis.lo): New dependences.
+
+ * configure.in: New bits for bfd_i860_arch.
+
+ * configure: Regenerated.
+
+2000-07-20 Hans-Peter Nilsson <hp@axis.com>
+
+ * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c.
+ (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo.
+ (cris-dis.lo, cris-opc.lo): New rules.
+ * Makefile.in: Rebuild.
+ * configure.in (bfd_cris_arch): New target.
+ * configure: Rebuild.
+ * disassemble.c (ARCH_cris): Define.
+ (disassembler): Support ARCH_cris.
+ * cris-dis.c, cris-opc.c: New files.
+ * po/POTFILES.in, po/opcodes.pot: Regenerate.
+
+2000-07-11 Jakub Jelinek <jakub@redhat.com>
+
+ * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
+ Reported by Bill Clarke <llib@computer.org>.
+
+2000-07-09 Geoffrey Keating <geoffk@cygnus.com>
+
+ * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
+ Patch by Randall J Fisher <rfisher@ecn.purdue.edu>.
+
+2000-07-09 Alan Modra <alan@linuxcare.com.au>
+
+ * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg,
+ fput_const, extract_3, extract_5_load, extract_5_store,
+ extract_5r_store, extract_5R_store, extract_10U_store,
+ extract_5Q_store, extract_11, extract_14, extract_16, extract_21,
+ extract_12, extract_17, extract_22): Prototype.
+ (print_insn_hppa): Rename inner block opcode -> opc to avoid
+ shadowing outer block.
+ (GET_BIT): Define.
+
+2000-07-05 DJ Delorie <dj@redhat.com>
+
+ * MAINTAINERS: new
+
+2000-07-04 Alexandre Oliva <aoliva@redhat.com>
+
+ * arm-dis.c (print_insn_arm): Output combinations of PSR flags.
+
+2000-07-03 Marek Michalkiewicz <marekm@linux.org.pl>
+
+ * avr-dis.c (avr_operand): Change _ () to _() around all strings
+ marked for translation (exception from the usual coding style).
+ (print_insn_avr): Initialize insn2 to avoid warnings.
+
+2000-07-03 Kazu Hirata <kazu@hxi.com>
+
+ * h8300-dis.c (bfd_h8_disassemble): Improve readability.
+ * h8500-dis.c: Fix formatting.
+
+2000-07-01 Alan Modra <alan@linuxcare.com.au>
+
+ * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed
+ (CLEANFILES): Add DEPA.
+ * Makefile.in: Regenerate.
+
+2000-06-26 Scott Bambrough <scottb@netwinder.org>
+
+ * arm-dis.c (regnames): Add an additional register set to match
+ the set used by GCC. Make it the default.
+
+2000-06-22 Alan Modra <alan@linuxcare.com.au>
+
+ * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we
+ find one.
+ * Makefile.in: Regenerate.
+
+2000-06-20 H.J. Lu <hjl@gnu.org>
+
+ * Makefile.am: Rebuild dependency.
+ * Makefile.in: Rebuild.
+
+2000-06-18 Stephane Carrez <stcarrez@worldnet.fr>
+
+ * Makefile.in, configure: regenerate
+ * disassemble.c (disassembler): Recognize ARCH_m68hc12,
+ ARCH_m68hc11.
+ * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12):
+ New functions.
+ * configure.in: Recognize m68hc12 and m68hc11.
+ * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x
+ * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
+ and opcode generation for m68hc11 and m68hc12.
+
+2000-06-16 Nick Duffek <nsd@redhat.com>
+
+ * disassemble.c (disassembler): Refer to the PowerPC 620 using
+ bfd_mach_ppc_620 instead of 620.
+
+2000-06-12 Kazu Hirata <kazu@hxi.com>
+
+ * h8300-dis.c: Fix formatting.
+ (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
+ correctly.
+
+Fri Jun 9 21:49:02 2000 Denis Chertykov <denisc@overta.ru>
+
+ * avr-dis.c (avr_operand): Bugfix for jmp/call address.
+
+Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
+
+ * avr-dis.c: completely rewritten.
+
+2000-06-02 Kazu Hirata <kazu@hxi.com>
+
+ * h8300-dis.c: Follow the GNU coding style.
+ (bfd_h8_disassemble) Fix a typo.
+
+2000-06-01 Kazu Hirata <kazu@hxi.com>
+
+ * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo.
+ (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
+ correctly. Fix a typo.
+
+2000-05-31 Nick Clifton <nickc@cygnus.com>
+
+ * opintl.h (_(String)): Explain why dgettext is used instead of
+ gettext.
+
+2000-05-30 Nick Clifton <nickc@cygnus.com>
+
+ * opintl.h (gettext, dgettext, dcgettext, textdomain,
+ bindtextdomain): Replace defines with those from intl/libgettext.h
+ to quieten gcc warnings.
+
+2000-05-26 Alan Modra <alan@linuxcare.com.au>
+
+ * Makefile.am: Update dependencies with "make dep-am"
+ * Makefile.in: Regenerate.
+
+Thu May 25 22:53:20 2000 Alexandre Oliva <aoliva@cygnus.com>
+
+ * m10300-dis.c (disassemble): Don't assume 32-bit longs when
+ sign-extending operands.
+
+Mon May 15 15:18:07 2000 Donald Lindsay <dlindsay@cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
+ except brf's.
+
+2000-05-21 Nick Clifton <nickc@cygnus.com>
+
+ * Makefile.am (LIBIBERTY): Define.
+
+Fri May 19 12:29:27 EDT 2000 Diego Novillo <dnovillo@redhat.com>
+
+ * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
+ (STD_REGISTER_NAMES): New name for REGISTER_NAMES.
+ (reg_names): Rename to std_reg_names. Change it to a char **
+ static variable.
+ (std_reg_names): New name for reg_names.
+ (set_mips_isa_type): Set reg_names to point to std_reg_names by
+ default.
+
+2000-05-16 Frank Ch. Eigler <fche@redhat.com>
+
+ * fr30-desc.h: Partially regenerated to account for changed
+ CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
+ * m32r-desc.h: Ditto.
+
+2000-05-15 Nick Clifton <nickc@cygnus.com>
+
+ * arm-opc.h: Use upper case for flasg in MSR and MRS
+ instructions. Allow any bit to be set in the field_mask of
+ the MSR instruction.
+
+ * arm-dis.c (print_insn_arm): Decode _x and _s bits of the
+ field_mask of an MSR instruction.
+
+2000-05-11 Thomas de Lellis <tdel@windriver.com>
+
+ * arm-opc.c: Disassembly of thumb ldsb/ldsh
+ instructions changed to ldrsb/ldrsh.
+
+2000-05-11 Ulf Carlsson <ulfc@engr.sgi.com>
+
+ * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
+ target addresses for 'jal' and 'j'.
+
+2000-05-10 Geoff Keating <geoffk@cygnus.com>
+
+ * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
+ also available in common mode when powerpc syntax is being used.
+
+2000-05-08 Alan Modra <alan@linuxcare.com.au>
+
+ * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
+ (dummy_print_address): Ditto.
+
+2000-05-04 Timothy Wall <twall@cygnus.com>
+
+ * tic54x-opc.c: New.
+ * tic54x-dis.c: New.
+ * disassemble.c (disassembler): Add ARCH_tic54x.
+ * configure.in: Added tic54x target.
+ * configure: Ditto.
+ * Makefile.am: Add tic54x dependencies.
+ * Makefile.in: Ditto.
+
+2000-05-03 J.T. Conklin <jtc@redback.com>
+
+ * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
+ vector unit operands.
+ (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
+ unit instruction formats.
+ (PPCVEC): New macro, mask for vector instructions.
+ (powerpc_operands): Add table entries for above operand types.
+ (powerpc_opcodes): Add table entries for vector instructions.
+
+ * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
+ (print_insn_little_powerpc): Likewise.
+ (print_insn_powerpc): Prepend 'v' when printing vector registers.
+
+Mon Apr 24 15:21:35 2000 Clinton Popetz <cpopetz@cygnus.com>
+
+ * configure.in: Add bfd_powerpc_64_arch.
+ * disassemble.c (disassembler): Use print_insn_big_powerpc for
+ 64 bit code.
+
+2000-04-24 Nick Clifton <nickc@cygnus.com>
+
+ * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
+ field.
+
+Sun Apr 23 17:54:14 2000 Denis Chertykov <denisc@overta.ru>
+
+ * avr-dis.c (reg_fmul_d): New. Extract destination register from
+ FMUL instruction.
+ (reg_fmul_r): New. Extract source register from FMUL instruction.
+ (reg_muls_d): New. Extract destination register from MULS instruction.
+ (reg_muls_r): New. Extract source register from MULS instruction.
+ (reg_movw_d): New. Extract destination register from MOVW instruction.
+ (reg_movw_r): New. Extract source register from MOVW instruction.
+ (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
+ EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
+
+2000-04-22 Timothy Wall <twall@cygnus.com>
+
+ * ia64-gen.c (general): Add an ordered table of primary
+ opcode names, as well as priority fields to disassembly data
+ structures to enforce a preferred disassembly format based on the
+ ordering of the opcode tables.
+ (load_insn_classes): Show a useful message if IC tables are missing.
+ (load_depfile): Ditto.
+ * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to
+ distinguish preferred disassembly.
+ * ia64-opc-f.c: Reorder some insn for preferred disassembly
+ format. Fix incorrect flag on fma.s/fma.s.s0.
+ * ia64-opc.c: Scan *all* disassembly matches and use the one with
+ the highest priority.
+ * ia64-opc-b.c: Use more abbreviations.
+ * ia64-asmtab.c: Regenerate.
+
+Fri Apr 21 16:03:39 2000 Jason Eckhardt <jle@cygnus.com>
+
+ * hppa-dis.c (extract_16): New function.
+ (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
+ new operand types l,y,&,fe,fE,fx.
+
+Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
+ David Mosberger <davidm@hpl.hp.com>
+ Timothy Wall <twall@cygnus.com>
+ Bob Manson <manson@charmed.cygnus.com>
+ Jim Wilson <wilson@cygnus.com>
+
+ * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
+ (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
+ ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
+ ia64-asmtab.c.
+ (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
+ (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
+ ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
+ * Makefile.in: Rebuild.
+ * configure Rebuild.
+ * configure.in (bfd_ia64_arch): New target.
+ * disassemble.c (ARCH_ia64): Define.
+ (disassembler): Support ARCH_ia64.
+ * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
+ ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
+ ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
+ ia64-war.tbl, ia64-waw.tbl): New files.
+
+2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
+
+ * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
+ (disassemble): Use them.
+
+2000-04-14 Alan Modra <alan@linuxcare.com.au>
+
+ * sysdep.h: Include "ansidecl.h" not <ansidecl.h>
+ * Makefile.am: Update dependencies.
+ * Makefile.in: Regenerate.
+
+2000-04-14 Michael Sokolov <msokolov@ivan.Harhan.ORG>
+
+ * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
+ avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
+ disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
+ i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
+ m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
+ mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c,
+ ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c,
+ tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c,
+ w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove
+ ansidecl.h as sysdep.h includes it.
+
+Fri Apr 7 15:56:57 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add
+ --enable-build-warnings option.
+ * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
+ * Makefile.in, configure: Re-generate.
+
+Wed Apr 5 22:28:18 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
+ stc GBR,@-<REG_N> is available for arch_sh1_up.
+ Group parallel processing insn with identical mnemonics together.
+ Make three-operand psha / pshl come first.
+
+Wed Apr 5 22:05:40 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
+ Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
+ (sh_arg_type): Add A_PC.
+ (sh_table): Update entries using immediates. Add repeat.
+ * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
+ Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
+
+2000-04-04 Alan Modra <alan@linuxcare.com.au>
+
+ * po/opcodes.pot: Regenerate.
+
+ * Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
+ (DEP): Quote when passing vars to sub-make. Add warning message
+ to end.
+ (DEP1): Rewrite for "gcc -MM".
+ (CLEANFILES): Add DEP2.
+ Update dependencies.
+ * Makefile.in: Regenerate.
+
+2000-04-03 Denis Chertykov <denisc@overta.ru>
+
+ * avr-dis.c: Syntax cleanup.
+ (add0fff): Print the pc relative address as a signed number.
+ (add03f8): Likewise.
+
+2000-04-01 Ian Lance Taylor <ian@zembu.com>
+
+ * disassemble.c (disassembler_usage): Don't use a prototype. Mark
+ the parameter ATTRIBUTE_UNUSED.
+ * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
+
+2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
+
+ * m10300-opc.c: SP-based offsets are always unsigned.
+
+2000-03-29 Thomas de Lellis <tdel@windriver.com>
+
+ * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
+ [branch always] instead of "undefined".
+
+2000-03-27 Nick Clifton <nickc@cygnus.com>
+
+ * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
+ short instructions, from end of list of long instructions.
+
+2000-03-27 Ian Lance Taylor <ian@zembu.com>
+
+ * Makefile.am (CFILES): Add avr-dis.c.
+ (ALL_MACHINES): Add avr-dis.lo.
+
+2000-03-27 Alan Modra <alan@linuxcare.com>
+
+ * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
+ truncate integers.
+ (print_insn_avr): Call function via pointer in K&R compatible way.
+ (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
+ add0fff, add03f8): Convert to old style function declaration and
+ add prototype.
+ (avrdis_opcode): Add prototype.
+
+2000-03-27 Denis Chertykov <denisc@overta.ru>
+
+ * avr-dis.c: New file. AVR disassembler.
+ * configure.in (bfd_avr_arch): New architecture support.
+ * disassemble.c: Likewise.
+ * configure: Regenerate.
+
+Mon Mar 6 19:52:05 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
+
+2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
+ flag to determine if operand is pc-relative.
+ * d30v-opc.c:
+ (d30v_format_table):
+ (REL6S3): Renamed from IMM6S3.
+ Added flag OPERAND_PCREL.
+ (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
+ added flag OPERAND_PCREL.
+ (IMM12S3U): Replaced with REL12S3.
+ (SHORT_D2, LONG_D): Delay target is pc-relative.
+ (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
+ Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
+ using the REL* operands.
+ (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
+ (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
+ LONG_Db, using REL* operands.
+ (SHORT_U, SHORT_A5S): Removed stray alternatives.
+ (d30v_opcode_table): Use new *r formats.
+
+2000-02-28 Nick Clifton <nickc@cygnus.com>
+
+ * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
+ 'signed_overflow_ok_p'.
+
+2000-02-27 Eli Zaretskii <eliz@is.elta.co.il>
+
+ * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
+ name of the libtool directory.
+ * Makefile.in: Rebuild.
+
+2000-02-24 Nick Clifton <nickc@cygnus.com>
+
+ * cgen-opc.c (cgen_set_signed_overflow_ok): New function.
+ (cgen_clear_signed_overflow_ok): New function.
+ (cgen_signed_overflow_ok_p): New function.
+
+2000-02-23 Andrew Haley <aph@cygnus.com>
+
+ * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
+ m32r-ibld.c,m32r-opc.h: Rebuild.
+
+2000-02-23 Linas Vepstas <linas@linas.org>
+
+ * i370-dis.c, i370-opc.c: New.
+
+ * disassemble.c (ARCH_i370): Define.
+ (disassembler): Handle it.
+
+ * Makefile.am: Add support for Linux/IBM 370.
+ * configure.in: Likewise.
+
+ * Makefile.in: Regenerate.
+ * configure: Likewise.
+
+2000-02-22 Chandra Chavva <cchavva@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
+ ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
+ procedure.
+
+1999-12-30 Andrew Haley <aph@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
+ force gp32 to zero.
+ * mips-opc.c (G6): New define.
+ (mips_builtin_op): Add "move" definition for -gp32.
+
+2000-02-22 Ian Lance Taylor <ian@zembu.com>
+
+ From Grant Erickson <gerickso@Brocade.COM>:
+ * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
+
+2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * dis-buf.c (buffer_read_memory): Change `length' param and all int
+ vars to unsigned.
+
+Thu Feb 17 00:18:12 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
+ (print_insn_ppi): Likewise.
+ (print_insn_shx): Use info->mach to select appropriate insn set.
+ Add support for sh-dsp. Remove FD_REG_N support.
+ * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
+ (sh_arg_type): Likewise. Remove FD_REG_N.
+ (sh_dsp_reg_nums): New enum.
+ (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
+ (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
+ (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
+ (arch_sh3_dsp_up): Likewise.
+ (sh_opcode_info): New field: arch.
+ (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
+ D_REG_N. Fill in arch field. Add sh-dsp insns.
+
+2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>
+
+ * arm-dis.c: Change flavor name from atpcs-special to
+ special-atpcs to prevent name conflict in gdb.
+ (get_arm_regname_num_options, set_arm_regname_option,
+ get_arm_regnames): New functions. API to access the several
+ flavor of register names. Note: Used by gdb.
+ (print_insn_thumb): Use the register name entry from the currently
+ selected flavor for LR and PC.
+
+2000-02-10 Nick Clifton <nickc@cygnus.com>
+
+ * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
+ classes.
+ (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
+ "mulsh.h" instructions.
+ * mcore-dis.c (imsk array): Add masks for MULSH and OPSR
+ classes.
+ (print_insn_mcore): Add support for little endian targets.
+ Add support for MULSH and OPSR classes.
+
+2000-02-07 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c (parse_arm_diassembler_option): Rename again.
+ Previous delat did not take.
+
+2000-02-03 Timothy Wall <twall@redhat.com>
+
+ * dis-buf.c (buffer_read_memory): Use octets_per_byte field
+ to adjust target address bounds checking and calculate the
+ appropriate octet offset into data.
+
+2000-01-27 Nick Clifton <nickc@redhat.com>
+
+ * arm-dis.c: (parse_disassembler_option): Rename to
+ parse_arm_disassembler_option and allow to be exported.
+
+ * disassemble.c (disassembler_usage): New function: Print out any
+ target specific disassembler options.
+ Call arm_disassembler_options() if the ARM architecture is being
+ supported.
+
+ * arm-dis.c (NUM_ELEM): Define this macro if not already
+ defined.
+ (arm_regname): New struct type for ARM register names.
+ (arm_toggle_regnames): Delete.
+ (parse_disassembler_option): Use register name structure.
+ (print_insn): New function: Combines duplicate code found in
+ print_insn_big_arm and print_insn_little_arm.
+ (print_insn_big_arm): Call print_insn.
+ (print_insn_little_arm): Call print_insn.
+ (print_arm_disassembler_options): Display list of supported,
+ ARM specific disassembler options.
+
+2000-01-27 Thomas de Lellis <tdel@windriver.com>
+
+ * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
+ ARM_STT_16BIT flag as Thumb code symbols.
+
+ * arm-dis.c (printf_insn_little_arm): Ditto.
+
+2000-01-25 Thomas de Lellis <tdel@windriver.com>
+
+ * arm-dis.c (printf_insn_thumb): Prevent double dumping
+ of raw thumb instructions.
+
+2000-01-20 Nick Clifton <nickc@cygnus.com>
+
+ * mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
+
+2000-01-03 Nick Clifton <nickc@cygnus.com>
+
+ * arm-dis.c (streq): New macro.
+ (strneq): New macro.
+ (force_thumb): ew local variable.
+ (parse_disassembler_option): New function: Parse a single, ARM
+ specific disassembler command line switch.
+ (parse_disassembler_option): Call parse_disassembler_option to
+ parse individual command line switches.
+ (print_insn_big_arm): Check force_thumb.
+ (print_insn_little_arm): Check force_thumb.
+
+1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall".
+
+Wed Dec 1 03:34:53 1999 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c, m10300-dis.c: Add am33 support.
+
+Wed Nov 24 20:29:58 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names.
+ (print_insn_hppa): Handle 'B' operand.
+
+1999-11-22 Nick Clifton <nickc@cygnus.com>
+
+ * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction.
+
+1999-11-18 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips-opc.c (I5): New.
+ (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
+ madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
+ pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
+
+Mon Nov 15 19:34:58 1999 Donald Lindsay <dlindsay@cygnus.com>
+
+ * arm-dis.c (print_insn_arm): Added general purpose 'X' format.
+ * arm-opc.h (print_insn_arm): Added comment documenting
+ the 'X' format just added to arm-dis.c.
+
+1999-11-15 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips-opc.c (la): Create a version that just uses addiu directly.
+ (dla): Expand to daddiu if possible.
+
+1999-11-11 Nick Clifton <nickc@cygnus.com>
+
+ * mips-opc.c: Add ssnop pattern.
+
+1999-11-01 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
+
+1999-10-29 Nick Clifton <nickc@cygnus.com>
+
+ * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA
+ (d30v_format_tab): Define the SHORT_AR format.
+
+1999-10-28 Nick Clifton <nickc@cygnus.com>
+
+ * mcore-dis.c: Remove spurious code introduced in previous delta.
+
+1999-10-27 Scott Bambrough <scottb@netwinder.org>
+
+ * arm-dis.c: Include sysdep.h to prevent compile time warnings.
+
+1999-10-18 Michael Meissner <meissner@cygnus.com>
+
+ * alpha-opc.c (alpha_operands): Fill in missing initializer.
+ (alpha_num_operands): Convert to unsigned.
+ (alpha_num_opcodes): Ditto.
+ (insert_rba): Declare unused arguments ATTRIBUTE_UNUSED.
+ (insert_rca): Ditto.
+ (insert_za): Ditto.
+ (insert_zb): Ditto.
+ (insert_zc): Ditto.
+ (extract_bdisp): Ditto.
+ (extract_jhint): Ditto.
+ (extract_ev6hwjhint): Ditto.
+
+Sun Oct 10 01:48:01 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org>
+
+ * hppa-dis.c (print_insn_hppa): Add new codes 'cc', 'cd', 'cC',
+ 'co', '@'.
+
+ * hppa-dis.c (print_insn_hppa): Removed unused args. Fix '?W'.
+
+ * hppa-dis.c (print_insn_hppa): Implement codes "?N", "?Q".
+
+Thu Oct 7 00:12:43 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
+
+ * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for
+ rac/rachi instructions.
+ (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi,
+ slae, st and st2w.
+
+1999-10-04 Doug Evans <devans@casey.cygnus.com>
+
+ * fr30-asm.c,fr30-desc.h: Rebuild.
+ * m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild. Add m32rx support.
+ * m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto.
+
+1999-09-29 Nick Clifton <nickc@cygnus.com>
+
+ * sh-opc.h: Fix bit patterns for several load and store
+ instructions.
+
+Thu Sep 23 08:27:20 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org
+
+ * hppa-dis.c (print_insn_hppa): Replace 'B', 'M', 'g' and 'l' with
+ cleaner code using completer prefixes. Add 'Y'.
+
+Sun Sep 19 10:41:27 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa-dis.c: (print_insn_hppa): Correct 'cJ', 'cc'.
+
+ * hppa-dis.c (extract_22): New function.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'J', 'K', and 'cc'.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'fe' and 'cJ'.
+
+ * hppa-dis.c (print_insn_hppa): Handle '#', 'd', and 'cq'.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'm', 'h', '='.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'X' operand.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'B' operand.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'M' and 'L' operands.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'l' operand.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'g' operand.
+
+Sat Sep 18 11:36:12 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa-dis.c (print_insn_hppa): Output a space after 'X' completer.
+
+ * hppa-dis.c: (print_insn_hppa): Do output a space before a 'v'
+ operand.
+
+ * hppa-dis.c: (print_insn_hppa): Handle 'fX'.
+
+ * hppa-dis.c: (print_insn_hppa): Add missing break after
+ FP register case.
+
+ * hppa-dis.c: Finish constifying various completers, register
+ names, etc etc.
+
+1999-09-14 Michael Meissner <meissner@cygnus.com>
+
+ * configure.in (Canonicalization of target names): Remove adding
+ ${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14
+ generates $ac_config_sub with a ${CONFIG_SHELL} already.
+ * configure: Regenerate.
+
+Tue Sep 7 13:50:32 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa-dis.c (print_insn_hppa): Escape '%' in output strings.
+
+ * hppa-dis.c (print_insn_hppa): Handle 'Z' argument.
+
+1999-09-07 Nick Clifton <nickc@cygnus.com>
+
+ * sh-opc.h: Add mulu.w and muls.w patterns. These are the correct
+ names for the mulu and muls patterns.
+
+1999-09-04 Steve Chamberlain <sac@pobox.com>
+
+ * pj-opc.c: New file.
+ * pj-dis.c: New file.
+ * disassemble.c (disassembler): Handle bfd_arch_pj.
+ * configure.in: Handle bfd_pj_arch.
+ * Makefile.am: Rebuild dependencies.
+ (CFILES): Add pj-dis.c and pj-opc.c.
+ (ALL_MACHINES): Add pj-dis.lo and pj-opc.lo.
+ * configure, Makefile.in: Rebuild.
+
+1999-09-04 H.J. Lu <hjl@gnu.org>
+
+ * i386-dis.c (print_insn_i386): Set bytes_per_line to 7.
+
+Mon Aug 30 18:56:14 1999 Richard Henderson <rth@cygnus.com>
+
+ * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31.
+
+1999-08-04 Doug Evans <devans@casey.cygnus.com>
+
+ * fr30-asm.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild.
+ * m32r-asm.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild.
+ * m32r-opinst.c: Rebuild.
+
+Sat Aug 28 00:27:24 1999 Jerry Quinn <jquinn@nortelnetworks.com>
+
+ * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float
+ register args by 'f'.
+
+ * hppa-dis.c (print_insn_hppa): Add args q, %, !, and |.
+
+ * hppa-dis.c (MASK_10, read_write_names, add_compl_names,
+ extract_10U_store): New.
+ (print_insn_hppa): Add new completers.
+
+ * hppa-dis.c (signed_unsigned_names,mix_half_names,
+ saturation_names): New.
+ (print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'.
+
+ * hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'.
+
+ * hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!'
+
+ * hppa-dis.c (print_insn_hppa): Look at next arg instead of bits
+ to decide to print a space.
+
+1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c: Add AMD athlon instruction support.
+
+1999-08-10 Ian Lance Taylor <ian@zembu.com>
+
+ From Wally Iimura <iimura@microunity.com>:
+ * dis-buf.c (buffer_read_memory): Rewrite expression to avoid
+ overflow at end of address space.
+ (generic_print_address): Use sprintf_vma.
+
+1999-08-08 Ian Lance Taylor <ian@zembu.com>
+
+ * Makefile.am: Rename .dep* files to DEP*. Change DEP variable to
+ MKDEP. Rebuild dependencies.
+ * Makefile.in: Rebuild.
+
+Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com>
+
+ * hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names,
+ add_cond_64_names, wide_add_cond_names, logical_cond_64_names,
+ unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New.
+ (print_insn_hppa): Add 64 bit condition completers.
+
+Thu Aug 5 16:59:58 1999 Jerry Quinn <jquinn@nortelnetworks.com>
+
+ * hppa-dis.c (print_insn_hppa): Change condition args to use
+ '?' prefix.
+
+Wed Jul 28 04:33:58 1999 Jerry Quinn <jquinn@nortelnetworks.com>
+
+ * hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E'
+ code.
+
+1999-07-21 Ian Lance Taylor <ian@zembu.com>
+
+ From Mark Elbrecht:
+ * configure.bat: Remove; obsolete.
+
+1999-07-11 Ian Lance Taylor <ian@zembu.com>
+
+ * dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate.
+ (generic_strcat_address): Add cast to avoid warning.
+ * i386-dis.c: Initialize all structure fields to avoid warnings.
+ Add ATTRIBUTE_UNUSED as appropriate.
+
+1999-07-08 Jakub Jelinek <jj@ultra.linux.cz>
+
+ * sparc-dis.c (print_insn_sparc): Differentiate between
+ addition and oring when guessing symbol for comment.
+
1999-07-05 Nick Clifton <nickc@cygnus.com>
* arm-dis.c (print_insn_arm): Display hex equivalent of rotated
- constant.
+ constant.
1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au>
1999-06-16 Nick Clifton <nickc@cygnus.com>
* arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange
- SWIs.
+ SWIs.
1999-06-14 Nick Clifton <nickc@cygnus.com> & Drew Mosley <dmoseley@cygnus.com>
* arm-dis.c (arm_regnames): Turn into a pointer to a register
name set.
(arm_regnames_standard): New variable: Array of ARM register
- names according to ARM instruction set nomenclature.
+ names according to ARM instruction set nomenclature.
(arm_regnames_apcs): New variable: Array of ARM register names
according to ARM Procedure Call Standard.
(arm_regnames_raw): New variable: Array of ARM register names
Mon Feb 1 20:54:36 1999 Catherine Moore <clm@cygnus.com>
- * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax.
- * i386-dis.c (x_mode): Define.
- (dis386): Remove.
- (dis386_att): New.
- (dis386_intel): New.
- (dis386_twobyte): Remove.
- (dis386_twobyte_att): New.
- (dis386_twobyte_intel): New.
- (print_insn_x86): Use new arrays.
- (float_mem): Remove.
- (float_mem_intel): New.
- (float_mem_att): New.
- (dofloat): Use new float_mem arrays.
- (print_insn_i386_att): New.
- (print_insn_i386_intel): New.
- (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax.
- (putop): Handle intel syntax.
- (OP_indirE): Handle intel syntax.
- (OP_E): Handle intel syntax.
- (OP_I): Handle intel syntax.
- (OP_sI): Handle intel syntax.
- (OP_OFF): Handle intel syntax.
-
-
+ * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax.
+ * i386-dis.c (x_mode): Define.
+ (dis386): Remove.
+ (dis386_att): New.
+ (dis386_intel): New.
+ (dis386_twobyte): Remove.
+ (dis386_twobyte_att): New.
+ (dis386_twobyte_intel): New.
+ (print_insn_x86): Use new arrays.
+ (float_mem): Remove.
+ (float_mem_intel): New.
+ (float_mem_att): New.
+ (dofloat): Use new float_mem arrays.
+ (print_insn_i386_att): New.
+ (print_insn_i386_intel): New.
+ (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax.
+ (putop): Handle intel syntax.
+ (OP_indirE): Handle intel syntax.
+ (OP_E): Handle intel syntax.
+ (OP_I): Handle intel syntax.
+ (OP_sI): Handle intel syntax.
+ (OP_OFF): Handle intel syntax.
1999-01-27 Doug Evans <devans@casey.cygnus.com>
* hppa-dis.c: revert HP merge changes until HP gives us
an updated file.
-
+
1999-01-19 Nick Clifton <nickc@cygnus.com>
* arm-dis.c (print_insn_arm): Display ARM syntax for PC relative
* dis-buf.c (generic_strcat_address): new function.
* hppa-dis.c: Changes to improve hppa disassembly.
- Changed formatting in : reg_names, fp_reg_names,control_reg,
+ Changed formatting in : reg_names, fp_reg_names,control_reg,
New variables : sign_extension_names, deposit_names, conversion_names
float_test_names, compare_cond_names_double, add_cond_names_double,
- logical_cond_names_double, unit_cond_names_double,
+ logical_cond_names_double, unit_cond_names_double,
branch_push_pop_names, saturation_names, shift_names, mix_names,
- New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG
+ New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG
Move some definitions to libhppa.h: GET_FIELD, GET_BIT
(fput_const): renamed as fput_hex_const
(print_insn_hppa):
- Some new code ifdefed for LOCAL_ONLY, all related to figuring out
architecture version number of current machine. HP folks are
trying to handle situation where the target program was compiled
- for PA 1.x (32-bit), but is running on a PA 2.0 machine and
+ for PA 1.x (32-bit), but is running on a PA 2.0 machine and
visa versa.
- added new cases : 'g', 'B', 'm'
- added cases specifically for PA 2.0
- - changed the following cases : '"', 'n', 'N', 'p', 'Z',
+ - changed the following cases : '"', 'n', 'N', 'p', 'Z',
- calls to fput_const become calls to fput_hex_const
1998-12-07 James E Wilson <wilson@wilson-pc.cygnus.com>
i960-dis.c to ta.
* i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig.
* i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.
-
+
Mon Dec 7 14:33:44 1998 Dave Brolley <brolley@cygnus.com>
* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
* fr30-opc.c: Regenerated.
Mon Nov 16 19:21:48 1998 Dave Brolley <brolley@cygnus.com>
-
+
* fr30-opc.c: Regenerated.
* fr30-opc.h: Regenerated.
* fr30-dis.c: Regenerated.
Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com>
* disassemble.c (disassembler): Add support for FR30 target.
-
+
Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild.
Mon Nov 2 15:05:33 1998 Geoffrey Noer <noer@cygnus.com>
- * configure.in: detect cygwin* instead of cygwin32*
- * configure: regenerate
+ * configure.in: detect cygwin* instead of cygwin32*
+ * configure: regenerate
Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com>
Thu Sep 24 09:20:03 1998 Nick Clifton <nickc@cygnus.com>
* d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP
- insns.
+ insns.
Tue Sep 22 17:55:14 1998 Nick Clifton <nickc@cygnus.com>
* d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit
- class.
+ class.
Tue Sep 15 15:14:45 1998 Doug Evans <devans@canuck.cygnus.com>
* arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf
object files.
(print_insn_little_arm): Detect Thumb symbols in elf object
- files.
+ files.
Sat Aug 29 22:24:09 1998 Richard Henderson <rth@cygnus.com>
Mon Aug 10 12:51:12 1998 Catherine Moore <clm@cygnus.com>
- * arm-dis.c (print_insn_big_arm): Fix indentation.
- (print_insn_little_arm): Likewise.
+ * arm-dis.c (print_insn_big_arm): Fix indentation.
+ (print_insn_little_arm): Likewise.
Sun Aug 9 20:17:28 1998 Catherine Moore <clm@cygnus.com>
- * arm-dis.c (print_insn_big_arm): Check for thumb symbol
- attributes.
- (print_insn_little_arm): Likewise.
+ * arm-dis.c (print_insn_big_arm): Check for thumb symbol
+ attributes.
+ (print_insn_little_arm): Likewise.
Mon Aug 3 12:43:16 1998 Doug Evans <devans@seba.cygnus.com>
* configure.in: For bfd_vax_arch, build vax-dis.lo.
* Makefile.am: Rebuild dependencies.
- (CFILES): Add vax-dis.c.
+ (CFILES): Add vax-dis.c.
(ALL_MACHINES): Add vax-dis.lo.
* aclocal.m4: Rebuild with current libtool.
* configure, Makefile.in: Rebuild.
Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com>
* mips-dis.c (print_insn_little_mips): Previously, instruction
- printing references the symbol table to determine whether the
- instruction resides in a block regular instructions or mips16
- instructions. However, when the disassembler gets used in other
- environments where the symbol table is not present, we no longer
- rely in the symbol table, rather, use the low bit of the
- instructions address to guess. There should be no change for usage
- of the disassembler in host based programs, gdb, objdump.
+ printing references the symbol table to determine whether the
+ instruction resides in a block regular instructions or mips16
+ instructions. However, when the disassembler gets used in other
+ environments where the symbol table is not present, we no longer
+ rely in the symbol table, rather, use the low bit of the
+ instructions address to guess. There should be no change for usage
+ of the disassembler in host based programs, gdb, objdump.
(print_insn_big_mips): ditto.
(print_insn_mips): ditto
(print_insn_x86): Cast to bfd_vma when passing a value to
print_address_func.
* ns32k-dis.c (CORE_ADDR): Don't define.
- (print_insn_ns32k): Change type of addr to bfd_vma. Use
+ (print_insn_ns32k): Change type of addr to bfd_vma. Use
bfd_scan_vma to read back address.
(print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma
to format it.
Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
* mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
- variety of ISA2 instructions to set bottom ten bits of trap code.
+ variety of ISA2 instructions to set bottom ten bits of trap code.
Thu May 7 11:54:25 1998 Ian Lance Taylor <ian@cygnus.com>
Wed Apr 1 16:20:27 1998 Ian Dall <Ian.Dall@dsto.defence.gov.au>
- * ns32k-dis.c (bit_extract_simple): New function to extract bits
- from an arbitrary valid buffer instead of fetching them on demand
- using fetch_data().
- (invalid_float): use bit_extract_simple() instead of bit_extract().
+ * ns32k-dis.c (bit_extract_simple): New function to extract bits
+ from an arbitrary valid buffer instead of fetching them on demand
+ using fetch_data().
+ (invalid_float): use bit_extract_simple() instead of bit_extract().
Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com>
* d10v-dis.c (PC_MASK): Correct value.
(print_operand): If there's a reloc, don't calculate the
- address because they could be in different sections.
+ address because they could be in different sections.
Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com>
* mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu"
- instruction after the 4650's "mul" instruction; nobody's using the
- 4010 these days. If object files someday indicate which processor
+ instruction after the 4650's "mul" instruction; nobody's using the
+ 4010 these days. If object files someday indicate which processor
variant they're intended for, we can do a better job at this.
Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com>
* tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
(tic80_opcodes): Reorder table entries to put the 32 bit PC relative
- offset forms before the 15 bit forms, to default to the long forms.
+ offset forms before the 15 bit forms, to default to the long forms.
Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com>
Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com>
* i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather
- than assuming that char is signed. Explicitly sign extend 16 bit
+ than assuming that char is signed. Explicitly sign extend 16 bit
values, rather than assuming that short is 16 bits.
(OP_sI, OP_J, OP_DIR): Likewise.
if an opcode has a short and a long form. Used for deciding
to append a ".s" or ".l".
(print_insn): Append a ".s" to an instruction if it is
- the short form and ".l" if it is a long form. Do not append
+ the short form and ".l" if it is a long form. Do not append
anything if the instruction has only one possible size.
* d30v-opc.c: Change mulx2h to require an even register.
Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com)
- * mn10200-dis.c (disassemble): PC relative instructions are
- relative to the next instruction, not the current instruction.
+ * mn10200-dis.c (disassemble): PC relative instructions are
+ relative to the next instruction, not the current instruction.
Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com>
Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com>
* ppc-opc.c (extract_nsi): make unsigned expression signed before
- negating it.
+ negating it.
(UNUSED): remove one level of parens, so MSVC doesn't choke on
- nesting depth when all the macros are expanded.
+ nesting depth when all the macros are expanded.
Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com>
Mon Mar 17 08:48:03 1997 J.T. Conklin <jtc@beauty.cygnus.com>
* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
- mulul insns on the coldfire.
+ mulul insns on the coldfire.
Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com>
Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com>
* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
- the mc68000.
+ the mc68000.
Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
(tic80_symbol_to_value): New function.
(tic80_value_to_symbol): New function.
* tic80-dis.c (print_operand_control_register,
- print_operand_condition_code, print_operand_bitnum):
+ print_operand_condition_code, print_operand_bitnum):
Remove private tables and use tic80_value_to_symbol function.
Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
(print_mips16_insn_arg): Likewise.
* mips-dis.c (print_insn_mips16): Better handling of an extend
- opcode followed by an instruction which can not be extended.
+ opcode followed by an instruction which can not be extended.
Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com>
* m68k-opc.c (m68k_opcodes): Changed operand specifier for the
- coldfire moveb instruction to not allow an address register as
- destination. Although the documentation does not indicate that
+ coldfire moveb instruction to not allow an address register as
+ destination. Although the documentation does not indicate that
this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation. Thanks to Andreas
Schwab for pointing this out to me.
Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com>
* tic80-opc.c (tic80_opcodes): Expand comment to note that the
- entries are presorted so that entries with the same mnemonic are
+ entries are presorted so that entries with the same mnemonic are
adjacent to each other in the table. Sort the entries for each
instruction so that this is true.
* tic80-opc.c (tic80_operands): Reorder some table entries to make
the order more logical. Move the shift alias instructions ("rotl",
"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
- interspersed with the regular sr.x and sl.x instructions. Add
+ interspersed with the regular sr.x and sl.x instructions. Add
and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
- "sub", "subu", "swcr", and "trap".
+ "sub", "subu", "swcr", and "trap".
Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com>
"ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr"
instructions.
* tic80-dis.c (print_insn_tic80): Print opcode name with fixed width
- 10 char field, padded with spaces on rhs, rather than a string
- followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
- than old TIC80_OPERAND_RELATIVE. Add support for new
+ 10 char field, padded with spaces on rhs, rather than a string
+ followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
+ than old TIC80_OPERAND_RELATIVE. Add support for new
TIC80_OPERAND_BASEREL flag bit.
Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
- in an instruction.
+ in an instruction.
* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
- Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
+ Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers.
(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
* Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
* disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
(disassembler): Add bfd_arch_tic80 support to set disassemble
- to print_insn_tic80.
+ to print_insn_tic80.
* tic80-dis.c (print_insn_tic80): Add stub.
Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com>
Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c: Add some comments explaining the various
- operands and such.
+ operands and such.
* mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com>
* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
- operand specifiers in *save, *restore and movem* instructions.
+ operand specifiers in *save, *restore and movem* instructions.
* m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
- the coldfire.
+ the coldfire.
* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
- register operands for immediate arithmetic, not, neg, negx, and
+ register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
- specifier of the effective-address operand in immediate forms of
- arithmetic instructions. The specifier for the immediate operand
- notes how and where the constant will be stored.
+ specifier of the effective-address operand in immediate forms of
+ arithmetic instructions. The specifier for the immediate operand
+ notes how and where the constant will be stored.
Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com)
Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
- sequential so the assembler never parallelizes it with
+ sequential so the assembler never parallelizes it with
other instructions.
Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com)
Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Move the fmovemx data register cases before the
- other cases, so that they get recognized before the data register
- does gets treated as a degenerate register list.
+ other cases, so that they get recognized before the data register
+ does gets treated as a degenerate register list.
Tue Sep 17 12:06:51 1996 Ian Lance Taylor <ian@cygnus.com>
Mon Sep 9 14:26:26 1996 Ian Lance Taylor <ian@cygnus.com>
* mips-dis.c (print_insn_arg): Print condition code registers as
- $fccN.
+ $fccN.
Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com>
Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com>
* v850-opc.c (v850_operands): Added insert and extract fields,
- pointers to functions that handle unusual operand encodings.
+ pointers to functions that handle unusual operand encodings.
Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com)
Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com>
* v850-opc.c (v850_operands): Add flags field.
- (v850_opcodes): add move opcodes.
+ (v850_opcodes): add move opcodes.
Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com>
Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com>
* i386-dis.c (print_insn_i386): Actually return the correct value.
- (ONE, OP_ONE): #ifdef out; not used.
+ (ONE, OP_ONE): #ifdef out; not used.
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk>
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
- memory transfer instructions. Add new format string entries %h and %s.
+ memory transfer instructions. Add new format string entries %h and %s.
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
- (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
+ (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com>
Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
- move ccr/sr insns more strict so that the disassembler only
- selects them when the addressing mode is data register.
+ move ccr/sr insns more strict so that the disassembler only
+ selects them when the addressing mode is data register.
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v-opc.c (pre_defined_registers): Declare.
- * d10v-dis.c (print_operand): Now uses pre_defined_registers
- to pick a better name for the registers.
+ * d10v-opc.c (pre_defined_registers): Declare.
+ * d10v-dis.c (print_operand): Now uses pre_defined_registers
+ to pick a better name for the registers.
Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com>
Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com>
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
- to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
+ to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com)
* ppc-opc.c (PPC860): Macro for 860/821 specific instructions and
registers.
- (powerpc_opcodes): Add 860/821 specific SPRs.
+ (powerpc_opcodes): Add 860/821 specific SPRs.
Mon Apr 8 14:00:44 1996 Ian Lance Taylor <ian@cygnus.com>
Fri Jan 12 14:35:58 1996 David Mosberger-Tang <davidm@AZStarNet.com>
* alpha-opc.h (alpha_insn_set): VAX floating point opcode was
- incorrectly defined as 0x16 when it should be 0x15.
+ incorrectly defined as 0x16 when it should be 0x15.
(FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits!
(alpha_insn_set): added cvtst and cvttq float ops. Also added
- excb (exception barrier) which is defined in the Alpha
- Architecture Handbook version 2.
+ excb (exception barrier) which is defined in the Alpha
+ Architecture Handbook version 2.
* alpha-dis.c (print_insn_alpha): Fixed special-case decoding for
- OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be
- disassembled as or, for example.
+ OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be
+ disassembled as or, for example.
Wed Jan 10 12:37:22 1996 Ian Lance Taylor <ian@cygnus.com>
* sh-opc.h (sh_nibble_type): Added REG_B.
(sh_arg_type): Added A_REG_B.
(sh_table): Added pref and bank reg versions of ldc, ldc.l, stc
- and stc.l opcodes.
+ and stc.l opcodes.
* sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B.
Fri Dec 15 16:44:31 1995 Ian Lance Taylor <ian@cygnus.com>
From David Mosberger-Tang <davidm@azstarnet.com>:
* alpha-dis.c (print_insn_alpha): fixed decoding of cpys
- instruction.
+ instruction.
Mon Dec 4 12:29:05 1995 J.T. Conklin <jtc@rtl.cygnus.com>
Mon Oct 23 11:11:34 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
* mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added
- the VR4100 specific instructions to the mips_opcodes structure.
+ the VR4100 specific instructions to the mips_opcodes structure.
Thu Oct 19 11:05:23 1995 Stan Shebs <shebs@andros.cygnus.com>
* m68k-dis.c (print_insn_m68k): Recognize all two-word
instructions that take no args by looking at the match mask.
- (print_insn_arg): Always print "%" before register names.
+ (print_insn_arg): Always print "%" before register names.
[case 'c']: Use "nc" for the no-cache case, as recognized by gas.
[case '_']: Don't print "@#" before address.
[case 'J']: Use "%s" as format string, not register name.
From David Mosberger-Tang <davidm@azstarnet.com>
* alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added.
- (alpha_insn_set): added definitions for VAX floating point
- instructions (Unix compilers don't generate these, but handcoded
- assembly might still use them).
+ (alpha_insn_set): added definitions for VAX floating point
+ instructions (Unix compilers don't generate these, but handcoded
+ assembly might still use them).
* alpha-dis.c (print_insn_alpha): added support for disassembling
- the miscellaneous instructions in the Alpha instruction set.
+ the miscellaneous instructions in the Alpha instruction set.
Tue Sep 26 18:47:20 1995 Stan Shebs <shebs@andros.cygnus.com>
Wed Feb 15 15:45:20 1995 Ian Lance Taylor <ian@cygnus.com>
* mips-opc.c: Add uld and usd macros for unaligned double load and
- store.
+ store.
Tue Feb 14 13:17:37 1995 Michael Meissner <meissner@tiktok.cygnus.com>
Thu Feb 9 12:28:13 1995 Stan Shebs <shebs@andros.cygnus.com>
* i960-dis.c (struct tabent, struct sparse_tabent): Change the
- signed char fields to shorts, more portable.
+ signed char fields to shorts, more portable.
Wed Feb 8 17:29:29 1995 Stan Shebs <shebs@andros.cygnus.com>
* i960-dis.c (struct tabent, struct sparse_tabent): Declare the
- char fields as signed chars, since they may have negative values.
+ char fields as signed chars, since they may have negative values.
Mon Feb 6 10:52:06 1995 J.T. Conklin <jtc@rtl.cygnus.com>
Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com)
- * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines
+ * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines
* z8kgen.c, z8k-opc.h: fix sizes of some shifts.
Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com)