+2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
+
+2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
+ (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
+ epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
+ (CLEANFILES): Add stamp-epiphany.
+ (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
+ (stamp-epiphany): New rule.
+ * configure.in: Handle bfd_epiphany_arch.
+ * disassemble.c (ARCH_epiphany): Define.
+ (disassembler): Handle bfd_arch_epiphany.
+ * epiphany-asm.c: New file.
+ * epiphany-desc.c: New file.
+ * epiphany-desc.h: New file.
+ * epiphany-dis.c: New file.
+ * epiphany-ibld.c: New file.
+ * epiphany-opc.c: New file.
+ * epiphany-opc.h: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
+2011-10-24 Julian Brown <julian@codesourcery.com>
+
+ * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
+
+2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
+
+ * s390-opc.txt: Add CPUMF instructions.
+
+2011-10-18 Jie Zhang <jie@codesourcery.com>
+ Julian Brown <julian@codesourcery.com>
+
+ * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
+
+2011-10-10 Nick Clifton <nickc@redhat.com>
+
+ * po/es.po: Updated Spanish translation.
+ * po/fi.po: Updated Finnish translation.
+
+2011-09-28 Jan Beulich <jbeulich@suse.com>
+
+ * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
+ RBX): New.
+ (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
+ (powerpc_opcodes): Use RAX for second and RBXC for third operand of
+ lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
+ lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
+ mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
+ on DFP quad instructions.
+
+2011-09-27 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (sparc_opcodes): Fix random instruction to write
+ to a float instead of an integer register.
+
+2011-09-26 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (sparc_opcodes): Add integer multiply-add
+ instructions.
+
+2011-09-21 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
+ bits. Fix "fchksm16" mnemonic.
+
+2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
+
+ The changes below bring 'mov' and 'ticc' instructions into line
+ with the V8 SPARC Architecture Manual.
+ * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
+ * sparc-opc.c (sparc_opcodes): Add alias entries for
+ 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
+ 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
+ * sparc-opc.c (sparc_opcodes): Move/Change entries for
+ 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
+ and 'mov imm,%tbr'.
+ * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
+ mov aliases.
+
+ * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
+ This has been reported as being accepted by the Sun assmebler.
+
+2011-09-08 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (pdistn): Destination is integer not float register.
+
+2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
+
+ PR gas/13145
+ * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
+
+2011-08-26 Nick Clifton <nickc@redhat.com>
+
+ * po/es.po: Updated Spanish translation.
+
+2011-08-22 Nick Clifton <nickc@redhat.com>
+
+ * Makefile.am (CPUDIR): Redfine to point to top level cpu
+ directory.
+ (stamp-frv): Use CPUDIR.
+ (stamp-iq2000): Likewise.
+ (stamp-lm32): Likewise.
+ (stamp-m32c): Likewise.
+ (stamp-mt): Likewise.
+ (stamp-xc16x): Likewise.
+ * Makefile.in: Regenerate.
+
+2011-08-09 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
+ and "mips64r2".
+ (print_insn_args, print_insn_micromips): Handle MCU.
+ * micromips-opc.c (MC): New macro.
+ (micromips_opcodes): Add "aclr", "aset" and "iret".
+ * mips-opc.c (MC): New macro.
+ (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
+
+2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
+ (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
+ (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
+ (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
+ (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
+ (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
+ (WR_s): Update macro.
+ (micromips_opcodes): Update register use flags of: "addiu",
+ "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
+ "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
+ "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
+ "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
+ "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
+ "swm" and "xor" instructions.
+
+2011-08-05 David S. Miller <davem@davemloft.net>
+
+ * sparc-dis.c (v9a_ast_reg_names): Add "cps".
+ (X_RS3): New macro.
+ (print_insn_sparc): Handle '4', '5', and '(' format codes.
+ Accept %asr numbers below 28.
+ * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
+ instructions.
+
+2011-08-02 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-dis.c (xop_table): Remove spurious bextr insn.
+
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13048
projects / deliverable / binutils-gdb.git / blobdiff