* simops.c: Include <sys/stat.h>.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 34fc60168ad2102dbff20a6c37dac12f3ddf6043..cb239a5546dcbf754583997d88eb3a6823b0a36c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,87 @@
+start-sanitize-v850
+Tue Oct 29 12:22:21 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * v850-opc.c (D9_RELAX): Renamed from D9, all references
+       changed.
+       (v850_operands): Make sure D22 immediately follows D9_RELAX.
+
+end-sanitize-v850
+Fri Oct 25 12:12:53 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5.
+
+start-sanitize-v850
+Thu Oct 24 17:53:52 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w
+       and sst.w instructions.
+
+       * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
+       "bCC"instructions).
+
+end-sanitize-v850
+Thu Oct 24 17:21:20 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * mips-dis.c (_print_insn_mips): Use a tab between the instruction
+       and the arguments.
+
+Tue Oct 22 23:32:56 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * ppc-opc.c (PPCPWR2): Define.
+       (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
+       it.
+
+Fri Oct 11 16:03:49 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
+       field for movhu instruction.
+start-sanitize-v850
+
+       * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
+       cast value to "long" not "signed long" to keep hpux10
+       compiler quiet.
+end-sanitize-v850
+
+Thu Oct 10 10:25:58 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
+       for mov (abs16),DN.
+
+       * mn10300-opc.c (FMT*): Remove definitions.
+
+       * mn10300-opc.c (mn10300_opcodes): Fix destination register
+       for shift-by-register opcodes.
+
+       * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
+       into [AD][MN][01] for encoding the position of the register
+       in the opcode.
+
+Wed Oct  9 11:19:26 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
+       "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
+       
+Tue Oct  8 11:55:35 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
+       Fix various typos.  Add "PAREN" operand.
+       (MEM, MEM2): Define.
+       (mn10300_opcodes): Surround all memory addresses with "PAREN"
+       operands.  Fix several typos.
+
+       * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
+       changes.
+
+Mon Oct  7 16:48:45 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (FMT_XX): Renumber starting at one.
+       (mn10300_operands): Rough cut.  Enough to parse "mov" instructions
+       at this time.
+       (mn10300_opcodes): Break opcode format out into its own field.
+       Update many operand fields to deal with signed vs unsigned
+       issues.  Fix one or two typos in the "mov" instruction
+       opcode, mask and/or operand fields.
+ 
 Mon Oct  7 11:39:49 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
 
        * m68k-opc.c (plusha): Prefer encoding for m68040up, in case