2006-02-24 David S. Miller <davem@sunset.davemloft.net>

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 629ab5e9bf77e7c2a03e3ef5bc8cdfc914e7f3dd..d97df75a4f496590dfa0361dca31b4415a7287c1 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,80 @@
+2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+
+       * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
+       (v9_hpriv_reg_names): New table.
+       (print_insn_sparc): Allow values up to 16 for '?' and '!'.
+       New cases '$' and '%' for read/write hyperprivileged register.
+       * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
+       window handling and rdhpr/wrhpr instructions.
+       
+2006-02-24  DJ Delorie  <dj@redhat.com>
+
+       * m32c-desc.c: Regenerate with linker relaxation attributes.
+       * m32c-desc.h: Likewise.
+       * m32c-dis.c: Likewise.
+       * m32c-opc.c: Likewise.
+
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+       * arm-dis.c (arm_opcodes): Add V7 instructions.
+       (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
+       (print_arm_address): New function.
+       (print_insn_arm): Use it.  Add 'P' and 'U' cases.
+       (psr_name): New function.
+       (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * ia64-opc-i.c (bXc): New.
+       (mXc): Likewise.
+       (OpX2TaTbYaXcC): Likewise.
+       (TF). Likewise.
+       (TFCM). Likewise.
+       (ia64_opcodes_i): Add instructions for tf.
+
+       * ia64-opc.h (IMMU5b): New.
+
+       * ia64-asmtab.c: Regenerated.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * ia64-gen.c: Update copyright years.
+       * ia64-opc-b.c: Likewise.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * ia64-gen.c (lookup_regindex): Handle ".vm".
+       (print_dependency_table): Handle '\"'.
+
+       * ia64-ic.tbl: Updated from SDM 2.2.
+       * ia64-raw.tbl: Likewise.
+       * ia64-waw.tbl: Likewise.
+       * ia64-asmtab.c: Regenerated.
+
+       * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+       * xc16x-desc.h: New file
+       * xc16x-desc.c: New file
+       * xc16x-opc.h: New file 
+       * xc16x-opc.c: New file
+       * xc16x-ibld.c: New file
+       * xc16x-asm.c: New file
+       * xc16x-dis.c: New file
+       * Makefile.am: Entries for xc16x 
+       * Makefile.in: Regenerate 
+       * cofigure.in: Add xc16x target information.
+       * configure: Regenerate.
+       * disassemble.c: Add xc16x target information.
+
+2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
+       moves.
+
 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c ('Z'): Add a new macro.