[AArch64][SVE 26/32] Add SVE MUL VL addressing modes

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a2afc0d77c6bdcdb710ae8701fdd177779280f32..de052a93540e0375384deb7f1fa7ca91c0bd950e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,92 @@
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
+       operands.
+       * aarch64-opc.c (aarch64_operand_modifiers): Initialize
+       the AARCH64_MOD_MUL_VL entry.
+       (value_aligned_p): Cope with non-power-of-two alignments.
+       (operand_general_constraint_met_p): Handle the new MUL VL addresses.
+       (print_immediate_offset_address): Likewise.
+       (aarch64_print_operand): Likewise.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
+       (ins_sve_addr_ri_s9xvl): New inserters.
+       * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
+       (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
+       (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
+       (ext_sve_addr_ri_s9xvl): New extractors.
+       * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
+       (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
+       (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
+       (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
+       * aarch64-dis-2.c: Regenerate.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
+       address operands.
+       * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
+       (FLD_SVE_xs_22): New aarch64_field_kinds.
+       (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
+       (get_operand_specific_data): New function.
+       * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
+       FLD_SVE_xs_14 and FLD_SVE_xs_22.
+       (operand_general_constraint_met_p): Handle the new SVE address
+       operands.
+       (sve_reg): New array.
+       (get_addr_sve_reg_name): New function.
+       (aarch64_print_operand): Handle the new SVE address operands.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
+       (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
+       (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
+       * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
+       (aarch64_ins_sve_addr_rr_lsl): Likewise.
+       (aarch64_ins_sve_addr_rz_xtw): Likewise.
+       (aarch64_ins_sve_addr_zi_u5): Likewise.
+       (aarch64_ins_sve_addr_zz): Likewise.
+       (aarch64_ins_sve_addr_zz_lsl): Likewise.
+       (aarch64_ins_sve_addr_zz_sxtw): Likewise.
+       (aarch64_ins_sve_addr_zz_uxtw): Likewise.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
+       (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
+       (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
+       * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
+       (aarch64_ext_sve_addr_ri_u6): Likewise.
+       (aarch64_ext_sve_addr_rr_lsl): Likewise.
+       (aarch64_ext_sve_addr_rz_xtw): Likewise.
+       (aarch64_ext_sve_addr_zi_u5): Likewise.
+       (aarch64_ext_sve_addr_zz): Likewise.
+       (aarch64_ext_sve_addr_zz_lsl): Likewise.
+       (aarch64_ext_sve_addr_zz_sxtw): Likewise.
+       (aarch64_ext_sve_addr_zz_uxtw): Likewise.
+       * aarch64-dis-2.c: Regenerate.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
+       AARCH64_OPND_SVE_PATTERN_SCALED.
+       * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
+       * aarch64-opc.c (fields): Add a corresponding entry.
+       (set_multiplier_out_of_range_error): New function.
+       (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
+       (operand_general_constraint_met_p): Handle
+       AARCH64_OPND_SVE_PATTERN_SCALED.
+       (print_register_offset_address): Use PRIi64 to print the
+       shift amount.
+       (aarch64_print_operand): Likewise.  Handle
+       AARCH64_OPND_SVE_PATTERN_SCALED.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-asm.h (ins_sve_scale): New inserter.
+       * aarch64-asm.c (aarch64_ins_sve_scale): New function.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis.h (ext_sve_scale): New inserter.
+       * aarch64-dis.c (aarch64_ext_sve_scale): New function.
+       * aarch64-dis-2.c: Regenerate.
+
 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 
        * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for