+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
+ operands.
+ * aarch64-opc.c (aarch64_operand_modifiers): Initialize
+ the AARCH64_MOD_MUL_VL entry.
+ (value_aligned_p): Cope with non-power-of-two alignments.
+ (operand_general_constraint_met_p): Handle the new MUL VL addresses.
+ (print_immediate_offset_address): Likewise.
+ (aarch64_print_operand): Likewise.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
+ (ins_sve_addr_ri_s9xvl): New inserters.
+ * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
+ (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
+ (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
+ (ext_sve_addr_ri_s9xvl): New extractors.
+ * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
+ (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
+ (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
+ (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
+ * aarch64-dis-2.c: Regenerate.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
+ address operands.
+ * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
+ (FLD_SVE_xs_22): New aarch64_field_kinds.
+ (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
+ (get_operand_specific_data): New function.
+ * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
+ FLD_SVE_xs_14 and FLD_SVE_xs_22.
+ (operand_general_constraint_met_p): Handle the new SVE address
+ operands.
+ (sve_reg): New array.
+ (get_addr_sve_reg_name): New function.
+ (aarch64_print_operand): Handle the new SVE address operands.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
+ (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
+ (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
+ * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
+ (aarch64_ins_sve_addr_rr_lsl): Likewise.
+ (aarch64_ins_sve_addr_rz_xtw): Likewise.
+ (aarch64_ins_sve_addr_zi_u5): Likewise.
+ (aarch64_ins_sve_addr_zz): Likewise.
+ (aarch64_ins_sve_addr_zz_lsl): Likewise.
+ (aarch64_ins_sve_addr_zz_sxtw): Likewise.
+ (aarch64_ins_sve_addr_zz_uxtw): Likewise.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
+ (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
+ (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
+ * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
+ (aarch64_ext_sve_addr_ri_u6): Likewise.
+ (aarch64_ext_sve_addr_rr_lsl): Likewise.
+ (aarch64_ext_sve_addr_rz_xtw): Likewise.
+ (aarch64_ext_sve_addr_zi_u5): Likewise.
+ (aarch64_ext_sve_addr_zz): Likewise.
+ (aarch64_ext_sve_addr_zz_lsl): Likewise.
+ (aarch64_ext_sve_addr_zz_sxtw): Likewise.
+ (aarch64_ext_sve_addr_zz_uxtw): Likewise.
+ * aarch64-dis-2.c: Regenerate.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
+ AARCH64_OPND_SVE_PATTERN_SCALED.
+ * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
+ * aarch64-opc.c (fields): Add a corresponding entry.
+ (set_multiplier_out_of_range_error): New function.
+ (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
+ (operand_general_constraint_met_p): Handle
+ AARCH64_OPND_SVE_PATTERN_SCALED.
+ (print_register_offset_address): Use PRIi64 to print the
+ shift amount.
+ (aarch64_print_operand): Likewise. Handle
+ AARCH64_OPND_SVE_PATTERN_SCALED.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm.h (ins_sve_scale): New inserter.
+ * aarch64-asm.c (aarch64_ins_sve_scale): New function.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_scale): New inserter.
+ * aarch64-dis.c (aarch64_ext_sve_scale): New function.
+ * aarch64-dis-2.c: Regenerate.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
+ AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
+ * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
+ (FLD_SVE_prfop): Likewise.
+ * aarch64-opc.c: Include libiberty.h.
+ (aarch64_sve_pattern_array): New variable.
+ (aarch64_sve_prfop_array): Likewise.
+ (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
+ (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
+ AARCH64_OPND_SVE_PRFOP.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
+ AARCH64_OPND_QLF_P_[ZM].
+ (aarch64_print_operand): Print /z and /m where appropriate.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
+ * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
+ (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
+ (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
+ (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
+ * aarch64-opc.c (fields): Add corresponding entries here.
+ (operand_general_constraint_met_p): Check that SVE register lists
+ have the correct length. Check the ranges of SVE index registers.
+ Check for cases where p8-p15 are used in 3-bit predicate fields.
+ (aarch64_print_operand): Handle the new SVE operands.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
+ * aarch64-asm.c (aarch64_ins_sve_index): New function.
+ (aarch64_ins_sve_reglist): Likewise.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
+ * aarch64-dis.c (aarch64_ext_sve_index): New function.
+ (aarch64_ext_sve_reglist): Likewise.
+ * aarch64-dis-2.c: Regenerate.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
+ (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
+ (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
+ * aarch64-opc.c (aarch64_match_operands_constraint): Check for
+ tied operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (get_offset_int_reg_name): New function.
+ (print_immediate_offset_address): Likewise.
+ (print_register_offset_address): Take the base and offset
+ registers as parameters.
+ (aarch64_print_operand): Update caller accordingly. Use
+ print_immediate_offset_address.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (BANK): New macro.
+ (R32, R64): Take a register number as argument
+ (int_reg): Use BANK.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (print_register_list): Add a prefix parameter.
+ (aarch64_print_operand): Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
+ for FPIMM.
+ * aarch64-asm.h (ins_fpimm): New inserter.
+ * aarch64-asm.c (aarch64_ins_fpimm): New function.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_fpimm): New extractor.
+ * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
+ (aarch64_ext_fpimm): New function.
+ * aarch64-dis-2.c: Regenerate.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-asm.c: Include libiberty.h.
+ (insert_fields): New function.
+ (aarch64_ins_imm): Use it.
+ * aarch64-dis.c (extract_fields): New function.
+ (aarch64_ext_imm): Use it.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
+ with an esize parameter.
+ (operand_general_constraint_met_p): Update accordingly.
+ Fix misindented code.
+ * aarch64-asm.c (aarch64_ins_limm): Update call to
+ aarch64_logical_immediate_p.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
+
+2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (find_format): Walk the linked list pointed by einsn.
+
+2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
+ xor3>: Delete mnemonics.
+ <cp_abort>: Rename mnemonic from ...
+ <cpabort>: ...to this.
+ <setb>: Change to a X form instruction.
+ <sync>: Change to 1 operand form.
+ <copy>: Delete mnemonic.
+ <copy_first>: Rename mnemonic from ...
+ <copy>: ...to this.
+ <paste, paste.>: Delete mnemonics.
+ <paste_last>: Rename mnemonic from ...
+ <paste.>: ...to this.
+
+2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
+
+2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-mkopc.c (main): Support alternate arch strings.
+
+2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
+
+ * s390-opc.txt: Fix kmctr instruction type.
+
+2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
+ * i386-init.h: Regenerated.
+
+2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * opcodes/arc-dis.c (print_insn_arc): Changed.
+
+2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
+ camellia_fl.
+
+2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (psr_name): Use hex as case labels. Add detection for
+ MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
+ FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
+
+2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
+ (PREFIX_MOD_3_0FAE_REG_4): Likewise.
+ (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
+ PREFIX_MOD_3_0FAE_REG_4.
+ (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
+ PREFIX_MOD_3_0FAE_REG_4.
+ * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
+ (cpu_flags): Add CpuPTWRITE.
+ * i386-opc.h (CpuPTWRITE): New.
+ (i386_cpu_flags): Add cpuptwrite.
+ * i386-opc.tbl: Add ptwrite instruction.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.h: Wrap around in extern "C".
+
+2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (V8_2_INSN): New macro.
+ (aarch64_opcode_table): Use it.
+
+2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Make more use of
+ CORE_INSN, __FP_INSN and SIMD_INSN.
+
+2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
+ (aarch64_opcode_table): Update uses accordingly.
+
+2016-07-25 Andrew Jenner <andrew@codesourcery.com>
+ Kwok Cheung Yeung <kcy@codesourcery.com>
+
+ opcodes/
+ * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
+ 'e_cmplwi' to 'e_cmpli' instead.
+ (OPVUPRT, OPVUPRT_MASK): Define.
+ (powerpc_opcodes): Add E200Z4 insns.
+ (vle_opcodes): Add context save/restore insns.
+
+2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
+
+ * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
+ "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
+ "j".
+
2016-07-27 Graham Markall <graham.markall@embecosm.com>
* arc-nps400-tbl.h: Change block comments to GNU format.