+start-sanitize-v850
+Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_opcodes): Add null opcode to mark the
+ end of the opcode table.
+
+end-sanitize-v850
+start-sanitize-d10v
+Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (pre_defined_registers): Added register pairs,
+ "r0-r1", "r2-r3", etc.
+
+end-sanitize-d10v
+start-sanitize-v850
+Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_operands): Make I16 be a signed operand.
+ Create I16U for an unsigned 16bit mmediate operand.
+ (v850_opcodes): Use I16U for "ori", "andi" and "xori".
+
+ * v850-opc.c (v850_operands): Define EP operand.
+ (IF4A, IF4B, IF4C, IF4D): Use EP.
+
+ * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"
+ with immediate operand, "movhi". Tweak "ldsr".
+
+ * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]
+ correct. Get sld.[bhw] and sst.[bhw] closer.
+
+ * v850-opc.c (v850_operands): "not" is a two byte insn
+
+ * v850-opc.c (v850_opcodes): Correct bit pattern for setf.
+
+ * v850-opc.c (v850_operands): D16 inserts at offset 16!
+
+ * v850-opc.c (two): Get order of words correct.
+
+ * v850-opc.c (v850_operands): I16 inserts at offset 16!
+
+ * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system
+ register source and destination operands.
+ (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
+
+ * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix
+ same thinko in "trap" opcode.
+
+ * v850-opc.c (v850_opcodes): Add initializer for size field
+ on all opcodes.
+
+ * v850-opc.c (v850_operands): D6 -> DS7. References changed.
+ Add D8 for 8-bit unsigned field in short load/store insns.
+ (IF4A, IF4D): These both need two registers.
+ (IF4C, IF4D): Define. Use 8-bit unsigned field.
+ (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
+ IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
+ for "ldsr" and "stsr".
+ * v850-opc.c (v850_operands): 3-bit immediate for bit insns
+ is unsigned.
+
+ * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
+ short store word (sst.w).
+
+Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * v850-opc.c (v850_operands): Added insert and extract fields,
+ pointers to functions that handle unusual operand encodings.
+
+Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_opcodes): Enable "trap".
+
+ * v850-opc.c (v850_opcodes): Fix order of displacement
+ and register for "set1", "clr1", "not1", and "tst1".
+
+Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_operands): Add "B3" support.
+ (v850_opcodes): Fix and enable "set1", "clr1", "not1"
+ and "tst1".
+
+ * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand.
+
+ * v850-opc.c: Close unterminated comment.
+
+Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com>
+
+ * v850-opc.c (v850_operands): Add flags field.
+ (v850_opcodes): add move opcodes.
+
+Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com>
+
+ * Makefile.in (ALL_MACHINES): Add v850-opc.o.
+ * configure: (bfd_v850v_arch) Add new case.
+ * configure.in: (bfd_v850_arch) Add new case.
+ * v850-opc.c: New file.
+
+end-sanitize-v850
+Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com>
+
+ * sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
+
start-sanitize-d10v
+Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c: Add additional information to the opcode
+ table to help determinine which instructions can be done
+ in parallel.
+
+end-sanitize-d10v
+Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com>
+
+ * mpw-make.sed: Update editing of include pathnames to be
+ more general.
+
+Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk>
+
+ * arm-opc.h: Added "bx" instruction definition.
+
+Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu>
+
+ * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
+
+start-sanitize-d10v
+Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
+
+Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
+
+end-sanitize-d10v
+Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de>
+
+ * makefile.vms: Update for alpha-opc changes.
+
+Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * i386-dis.c (print_insn_i386): Actually return the correct value.
+ (ONE, OP_ONE): #ifdef out; not used.
+
+start-sanitize-d10v
+Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
+ Changed subi operand type to treat 0 as 16.
+
+end-sanitize-d10v
+Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose
+ <rose@netcom.com>.
+
+Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk>
+
+ * arm-opc.h: (arm_opcodes): Added halfword and sign-extension
+ memory transfer instructions. Add new format string entries %h and %s.
+ * arm-dis.c: (print_insn_arm): Provide decoding of the new
+ formats %h and %s.
+
+start-sanitize-d10v
+Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
+ (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
+
+end-sanitize-d10v
+Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * alpha-dis.c (print_insn_alpha_osf): Remove.
+ (print_insn_alpha_vms): Remove.
+ (print_insn_alpha): Make globally visible. Chose the register
+ names based on info->flavour.
+ * disassemble.c: Always return print_insn_alpha for the alpha.
+
+start-sanitize-d10v
+Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c (dis_long): Handle unknown opcodes.
+
Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c: Changes to support signed and unsigned numbers.
projects / deliverable / binutils-gdb.git / blobdiff