+2016-12-29 Yao Qi <yao.qi@linaro.org>
+
+ * avr-dis.c: Include "bfd_stdint.h"
+ (avrdis_opcode): Change return type to int, add argument
+ insn. Set *INSN on success.
+ (print_insn_avr): Check return value of avrdis_opcode, and
+ return -1 on error.
+
+2016-12-28 Alan Modra <amodra@gmail.com>
+
+ * configure.ac: Revert 2016-12-23.
+ * Makefile.am: Likewise.
+ (MIPS_DEFS): Define.
+ (mips-dis.lo): Add rule.
+ * Makefile.in: Regenerate.
+ * aclocal.m4: Regenerate.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
+ `4' and `s' operand codes.
+ (mips16_opcodes): Add "asmacro" entry.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Simplify processing of
+ extended operands.
+ * mips16-opc.c (decode_mips16_operand): Switch the extended
+ form of the `<' operand type to LSB position 22.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
+ operand codes with `.' and `F' respectively.
+ (mips16_opcodes): Likewise.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
+ matching for INSN2_SHORT_ONLY opcode table entries.
+ * mips16-opc.c (SH): New macro.
+ (mips16_opcodes): Set SH in `pinfo2' for non-extensible
+ instruction entries: "nop", "addu", "and", "break", "cmp",
+ "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
+ "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
+ "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
+ "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
+ "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
+ "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
+ "seh", "sew", "zeb", "zeh", "zew" and "extend".
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
+ encoding support.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
+ "extend".
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (set_default_mips_dis_options): Use
+ HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
+ call to `bfd_mips_elf_get_abiflags'.
+ * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
+ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * Makefile.in: Regenerate.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * po/opcodes.pot: Regenerate.
+
+2016-12-21 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
+ ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
+ (print_insn_mips16): Check opcode entries for validity against
+ the ISA level and ASE set selected.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
+ `insn' together, with `extend' as the high-order 16 bits.
+ (match_kind): New enum.
+ (print_insn_mips16): Rework for 32-bit instruction matching.
+ Do not dump EXTEND prefixes here.
+ * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
+ Recode `match' and `mask' fields as 32-bit in absolute "jal" and
+ "jalx" entries.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+ than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
+ INSN_MACRO entries.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+ than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
+ opcode).
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
+ "*.aqrl".
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
+ INSN_ALIAS.
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
+ format.
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
+ XLEN when none is provided.
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c: Formatting fixes.
+
+2016-12-20 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
+ Only examine ELF file structures here.
+
+2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
+ `bfd_mips_elf_get_abiflags' here.
+
+2016-12-16 Nick Clifton <nickc@redhat.com>
+
+ * arm-dis.c (print_insn_thumb32): Fix compile time warning
+ computing value_in_comment.
+
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (mips_convert_abiflags_ases): New function.
+ (set_default_mips_dis_options): Also infer ASE flags from ELF
+ file structures.
+
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
+ header flag interpretation code.
+
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
+ `pinfo2' with SP-relative "sd" entries.
+
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
+ compact jumps.
+
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+ * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
+ qualifier.
+ (operand_general_constraint_met_p): Remove case for CP_REG.
+ (aarch64_print_operand): Print CRn, CRm operand using imm field.
+ * aarch64-tbl.h (QL_SYS): Use CR qualifier.
+ (QL_SYSL): Likewise.
+ (aarch64_opcode_table): Change CRn, CRm operand class and type.
+ * aarch64-opc-2.c : Regenerate.
+ * aarch64-asm-2.c : Likewise.
+ * aarch64-dis-2.c : Likewise.
+
+2016-12-12 Yao Qi <yao.qi@linaro.org>
+
+ * rx-dis.c: Include <setjmp.h>
+ (struct private): New.
+ (rx_get_byte): Check return value of read_memory_func, and
+ call memory_error_func and OPCODES_SIGLONGJMP on error.
+ (print_insn_rx): Call OPCODES_SIGSETJMP.
+
+2016-12-12 Yao Qi <yao.qi@linaro.org>
+
+ * rl78-dis.c: Include <setjmp.h>.
+ (struct private): New.
+ (rl78_get_byte): Check return value of read_memory_func, and
+ call memory_error_func and OPCODES_SIGLONGJMP on error.
+ (print_insn_rl78_common): Call OPCODES_SIGJMP.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
+ than UINT.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_mips16): Use a tab rather than a space
+ to separate `extend' and its uninterpreted argument output.
+ Separate hexadecimal halves of undecoded extended instructions
+ output.
+
2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_mips16_insn_arg): Remove extraneous
projects / deliverable / binutils-gdb.git / blobdiff