+2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
+
+2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
+
+2005-01-10 Andreas Schwab <schwab@suse.de>
+
+ * disassemble.c (disassemble_init_for_target) <case
+ bfd_arch_ia64>: Set skip_zeroes to 16.
+ <case bfd_arch_tic4x>: Set skip_zeroes to 32.
+
+2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
+
+2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * avr-dis.c: Prettyprint. Added printing of symbol names in all
+ memory references. Convert avr_operand() to C90 formatting.
+
+2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
+
+2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
+ (no_op_insn): Initialize array with instructions that have no
+ operands.
+ * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
+
+2004-11-29 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm-dis.c: Correct top-level comment.
+
+2004-11-27 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
+ architecuture defining the insn.
+ (arm_opcodes, thumb_opcodes): Delete. Move to ...
+ * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
+ field.
+ Also include opcode/arm.h.
+ * Makefile.am (arm-dis.lo): Update dependency list.
+ * Makefile.in: Regenerate.
+
+2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
+
+ * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
+ reflect the change to the short immediate syntax.
+
+2004-11-19 Alan Modra <amodra@bigpond.net.au>
+
+ * or32-opc.c (debug): Warning fix.
+ * po/POTFILES.in: Regenerate.
+
+ * maxq-dis.c: Formatting.
+ (print_insn): Warning fix.
+
+2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * arm-dis.c (WORD_ADDRESS): Define.
+ (print_insn): Use it. Correct big-endian end-of-section handling.
+
+2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
+ Vineet Sharma <vineets@noida.hcltech.com>
+
+ * maxq-dis.c: New file.
+ * disassemble.c (ARCH_maxq): Define.
+ (disassembler): Add 'print_insn_maxq_little' for handling maxq
+ instructions..
+ * configure.in: Add case for bfd_maxq_arch.
+ * configure: Regenerate.
+ * Makefile.am: Add support for maxq-dis.c
+ * Makefile.in: Regenerate.
+ * aclocal.m4: Regenerate.
+
+2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
+ mode.
+ * crx-dis.c: Likewise.
+
+2004-11-04 Hans-Peter Nilsson <hp@axis.com>
+
+ Generally, handle CRISv32.
+ * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
+ (struct cris_disasm_data): New type.
+ (format_reg, format_hex, cris_constraint, print_flags)
+ (get_opcode_entry): Add struct cris_disasm_data * parameter. All
+ callers changed.
+ (format_sup_reg, print_insn_crisv32_with_register_prefix)
+ (print_insn_crisv32_without_register_prefix)
+ (print_insn_crisv10_v32_with_register_prefix)
+ (print_insn_crisv10_v32_without_register_prefix)
+ (cris_parse_disassembler_options): New functions.
+ (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
+ parameter. All callers changed.
+ (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
+ failure.
+ (cris_constraint) <case 'Y', 'U'>: New cases.
+ (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
+ for constraint 'n'.
+ (print_with_operands) <case 'Y'>: New case.
+ (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
+ <case 'N', 'Y', 'Q'>: New cases.
+ (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
+ (print_insn_cris_with_register_prefix)
+ (print_insn_cris_without_register_prefix): Call
+ cris_parse_disassembler_options.
+ * cris-opc.c (cris_spec_regs): Mention that this table isn't used
+ for CRISv32 and the size of immediate operands. New v32-only
+ entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
+ spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
+ ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
+ Change brp to be v3..v10.
+ (cris_support_regs): New vector.
+ (cris_opcodes): Update head comment. New format characters '[',
+ ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
+ Add new opcodes for v32 and adjust existing opcodes to accommodate
+ differences to earlier variants.
+ (cris_cond15s): New vector.
+
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
+ (indirEb): Remove.
+ (Mp): Use f_mode rather than none at all.
+ (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
+ replaces what previously was x_mode; x_mode now means 128-bit SSE
+ operands.
+ (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
+ mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
+ pinsrw's second operand is Edqw.
+ (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
+ operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
+ fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
+ mode when an operand size override is present or always suffixing.
+ More instructions will need to be added to this group.
+ (putop): Handle new macro chars 'C' (short/long suffix selector),
+ 'I' (Intel mode override for following macro char), and 'J' (for
+ adding the 'l' prefix to far branches in AT&T mode). When an
+ alternative was specified in the template, honor macro character when
+ specified for Intel mode.
+ (OP_E): Handle new *_mode values. Correct pointer specifications for
+ memory operands. Consolidate output of index register.
+ (OP_G): Handle new *_mode values.
+ (OP_I): Handle const_1_mode.
+ (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
+ respective opcode prefix bits have been consumed.
+ (OP_EM, OP_EX): Provide some default handling for generating pointer
+ specifications.
+
+2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
+ COP_INST macro.
+
+2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
+ (getregliststring): Support HI/LO and user registers.
+ * crx-opc.c (crx_instruction): Update data structure according to the
+ rearrangement done in CRX opcode header file.
+ (crx_regtab): Likewise.
+ (crx_optab): Likewise.
+ (crx_instruction): Reorder load/stor instructions, remove unsupported
+ formats.
+ support new Co-Processor instruction 'cpi'.
+
+2004-10-27 Nick Clifton <nickc@redhat.com>
+
+ * opcodes/iq2000-asm.c: Regenerate.
+ * opcodes/iq2000-desc.c: Regenerate.
+ * opcodes/iq2000-desc.h: Regenerate.
+ * opcodes/iq2000-dis.c: Regenerate.
+ * opcodes/iq2000-ibld.c: Regenerate.
+ * opcodes/iq2000-opc.c: Regenerate.
+ * opcodes/iq2000-opc.h: Regenerate.
+
+2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
+ us4, us5 (respectively).
+ Remove unsupported 'popa' instruction.
+ Reverse operands order in store co-processor instructions.
+
+2004-10-15 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am"
+ * Makefile.in: Regenerate.
+
+2004-10-12 Bob Wilson <bob.wilson@acm.org>
+
+ * xtensa-dis.c: Use ISO C90 formatting.
+
+2004-10-09 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c: Revert 2004-09-09 change.
+
2004-10-07 Bob Wilson <bob.wilson@acm.org>
* xtensa-dis.c (state_names): Delete.
projects / deliverable / binutils-gdb.git / blobdiff