2005-01-14 Andrew Cagney <cagney@gnu.org>

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 550bffab927ea7f0c31acfedcfc4d1c5d6b50c2d..f4edcb3dcadf5f435629807fbff418aaa834bd77 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,89 @@
+2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
+
+2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
+
+2005-01-10  Andreas Schwab  <schwab@suse.de>
+
+       * disassemble.c (disassemble_init_for_target) <case
+       bfd_arch_ia64>: Set skip_zeroes to 16.
+       <case bfd_arch_tic4x>: Set skip_zeroes to 32.
+
+2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
+
+       * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
+
+2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+       * avr-dis.c: Prettyprint. Added printing of symbol names in all
+       memory references. Convert avr_operand() to C90 formatting.
+
+2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
+
+       * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
+
+2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
+
+       * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
+       (no_op_insn): Initialize array with instructions that have no
+       operands.
+       * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
+
+2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm-dis.c: Correct top-level comment.
+
+2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
+       architecuture defining the insn.
+       (arm_opcodes, thumb_opcodes): Delete.  Move to ...
+       * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
+       field.
+       Also include opcode/arm.h.
+       * Makefile.am (arm-dis.lo): Update dependency list.
+       * Makefile.in: Regenerate.
+
+2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
+
+       * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
+       reflect the change to the short immediate syntax.
+
+2004-11-19  Alan Modra  <amodra@bigpond.net.au>
+
+       * or32-opc.c (debug): Warning fix.
+       * po/POTFILES.in: Regenerate.
+
+       * maxq-dis.c: Formatting.
+       (print_insn): Warning fix.
+
+2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
+
+       * arm-dis.c (WORD_ADDRESS): Define.
+       (print_insn): Use it.  Correct big-endian end-of-section handling.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+           Vineet Sharma      <vineets@noida.hcltech.com>
+
+       * maxq-dis.c: New file.
+       * disassemble.c (ARCH_maxq): Define.
+       (disassembler): Add 'print_insn_maxq_little' for handling maxq
+       instructions..
+       * configure.in: Add case for bfd_maxq_arch.
+       * configure: Regenerate.
+       * Makefile.am: Add support for maxq-dis.c
+       * Makefile.in: Regenerate.
+       * aclocal.m4: Regenerate.
+
+2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
+
+       * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
+       mode.
+       * crx-dis.c: Likewise.
+
 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 
        Generally, handle CRISv32.