Arm64: correct address index operands for LD1RO{H,W,D}

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ec6451271c9621f896956f2b2c7b80177f932bdf..fb9f9e0929e334833ee7ba9f09ded58d28ee906a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,12 +1,22 @@
 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 
-       * opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
+       * aarch64-tbl.h (aarch64_opcode_table): Use
+       SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
+
+2020-01-03  Jan Beulich  <jbeulich@suse.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
+       forms of SUDOT and USDOT.
+
+2020-01-03  Jan Beulich  <jbeulich@suse.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
        uzip{1,2}.
        * opcodes/aarch64-dis-2.c: Re-generate.
 
 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 
-       * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
+       * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
        FMMLA encoding.
        * opcodes/aarch64-dis-2.c: Re-generate.