HFILES = \
arm-opc.h \
fr30-desc.h fr30-opc.h \
+ frv-desc.h frv-opc.h \
h8500-opc.h \
ia64-asmtab.h \
ia64-opc.h \
fr30-dis.c \
fr30-ibld.c \
fr30-opc.c \
+ frv-asm.c \
+ frv-desc.c \
+ frv-dis.c \
+ frv-ibld.c \
+ frv-opc.c \
h8300-dis.c \
h8500-dis.c \
hppa-dis.c \
fr30-dis.lo \
fr30-ibld.lo \
fr30-opc.lo \
+ frv-asm.lo \
+ frv-desc.lo \
+ frv-dis.lo \
+ frv-ibld.lo \
+ frv-opc.lo \
h8300-dis.lo \
h8500-dis.lo \
hppa-dis.lo \
POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
- stamp-m32r stamp-fr30 stamp-openrisc \
+ stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \
stamp-xstormy16 \
libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi`
CGENFLAGS = -v
-CGENDEPS = ../cgen/stamp-cgen \
+CGENDEPS = \
$(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \
$(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \
$(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \
@CGEN_MAINT_FALSE@M32R_DEPS =
@CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30
@CGEN_MAINT_FALSE@FR30_DEPS =
+@CGEN_MAINT_TRUE@FRV_DEPS = @CGEN_MAINT_TRUE@stamp-frv
+@CGEN_MAINT_FALSE@FRV_DEPS =
@CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc
@CGEN_MAINT_FALSE@OPENRISC_DEPS =
@CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
-TAR = gtar
+TAR = tar
GZIP_ENV = --best
SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
$(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles=
+$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS)
+ @true
+stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc
+ $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles=
+
$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
@true
stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/d30v.h
dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
- $(INCDIR)/opcode/dlx.h $(INCDIR)/dis-asm.h $(BFD_H) \
- $(INCDIR)/symcat.h opintl.h
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h
dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
fr30-opc.h $(INCDIR)/libiberty.h
+frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \
+ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \
+ $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h
+frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \
+ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \
+ $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h
+frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h \
+ $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \
+ frv-opc.h opintl.h
+frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+ $(BFD_H) $(INCDIR)/ansidecl.h \
+ $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \
+ frv-opc.h opintl.h
+frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \
+ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \
+ $(INCDIR)/opcode/cgen.h frv-opc.h
h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/symcat.h opintl.h