[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt operand...

[deliverable/binutils-gdb.git] / opcodes / aarch64-asm.h

diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 3211aff99b4c5dd2267f4744053f464fa2f800eb..0cce71c42a853f6bdd8c383308fe614fc87c1a61 100644 (file)
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -54,6 +54,7 @@ AARCH64_DECL_OPD_INSERTER (ins_fpimm);
 AARCH64_DECL_OPD_INSERTER (ins_fbits);
 AARCH64_DECL_OPD_INSERTER (ins_aimm);
 AARCH64_DECL_OPD_INSERTER (ins_limm);
+AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
 AARCH64_DECL_OPD_INSERTER (ins_ft);
 AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
 AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
@@ -69,6 +70,27 @@ AARCH64_DECL_OPD_INSERTER (ins_hint);
 AARCH64_DECL_OPD_INSERTER (ins_prfop);
 AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
 AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_u6);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rr_lsl);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rz_xtw);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zi_u5);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
+AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
+AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
+AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
+AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
+AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
+AARCH64_DECL_OPD_INSERTER (ins_sve_index);
+AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
+AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
+AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
+AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
+AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
 
 #undef AARCH64_DECL_OPD_INSERTER