gdb/configure.ac: add --enable-source-highlight

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 38d48225bfdd6bfe8768fdd433a2f1c1c88a9ae0..277fa7bf84f7c95372417c6fa6c580a1b1ec0cef 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -320,6 +320,7 @@ const aarch64_field fields[] =
     { 13,  2 }, /* rotate2: Indexed element FCMLA immediate rotate.  */
     { 12,  1 }, /* rotate3: FCADD immediate rotate.  */
     { 12,  2 }, /* SM3: Indexed element SM3 2 bits index immediate.  */
+    { 22,  1 }, /* sz: 1-bit element size select.  */
 };
 
 enum aarch64_operand_class
@@ -1602,7 +1603,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
          break;
        case ldst_imm9:
        case ldstpair_indexed:
-       case ldstgv_indexed:
        case asisdlsep:
        case asisdlsop:
          if (opnd->addr.writeback == 0)
@@ -3156,6 +3156,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 
     case AARCH64_OPND_Rd_SP:
     case AARCH64_OPND_Rn_SP:
+    case AARCH64_OPND_Rt_SP:
     case AARCH64_OPND_SVE_Rn_SP:
     case AARCH64_OPND_Rm_SP:
       assert (opnd->qualifier == AARCH64_OPND_QLF_W
@@ -3557,11 +3558,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
        snprintf (buf, size, "[%s]", name);
       break;
 
-    case AARCH64_OPND_ADDR_SIMPLE_2:
-      name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
-      snprintf (buf, size, "[%s]!", name);
-      break;
-
     case AARCH64_OPND_ADDR_REGOFF:
     case AARCH64_OPND_SVE_ADDR_R:
     case AARCH64_OPND_SVE_ADDR_RR:
@@ -4734,6 +4730,29 @@ verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
   return ERR_OK;
 }
 
+/* Verifier for vector by element 3 operands functions where the
+   conditions `if sz:L == 11 then UNDEFINED` holds.  */
+
+static enum err_type
+verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
+               bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
+               aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
+               aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
+{
+  const aarch64_insn undef_pattern = 0x3;
+  aarch64_insn value;
+
+  assert (inst->opcode);
+  assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
+  value = encoding ? inst->value : insn;
+  assert (value);
+
+  if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
+    return ERR_UND;
+
+  return ERR_OK;
+}
+
 /* Initialize an instruction sequence insn_sequence with the instruction INST.
    If INST is NULL the given insn_sequence is cleared and the sequence is left
    uninitialized.  */
@@ -4910,6 +4929,7 @@ verify_constraints (const struct aarch64_inst *inst,
                  case AARCH64_OPND_Rn:
                  case AARCH64_OPND_Rm:
                  case AARCH64_OPND_Rn_SP:
+                 case AARCH64_OPND_Rt_SP:
                  case AARCH64_OPND_Rm_SP:
                    if (inst_op.reg.regno == blk_dest.reg.regno)
                      {