{ 31, 1 }, /* b5: in the test bit and branch instructions. */
{ 19, 5 }, /* b40: in the test bit and branch instructions. */
{ 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
+ { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
+ { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
+ { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
{ 17, 1 }, /* SVE_N: SVE equivalent of N. */
{ 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
{ 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
{ 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
{ 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
{ 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
+ { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
+ { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
+ { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
+ { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
+ { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
{ 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
{ 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
{ 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
{ 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
{ 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
{ 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
+ { 22, 1 }, /* SVE_sz: 1-bit element size select. */
+ { 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
+ { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
+ { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
{ 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
{ 22, 1 } /* SVE_xs_22: UXTW/SXTW select (bit 22). */
};
/* Table of all conditional affixes. */
const aarch64_cond aarch64_conds[16] =
{
- {{"eq"}, 0x0},
- {{"ne"}, 0x1},
- {{"cs", "hs"}, 0x2},
- {{"cc", "lo", "ul"}, 0x3},
- {{"mi"}, 0x4},
- {{"pl"}, 0x5},
+ {{"eq", "none"}, 0x0},
+ {{"ne", "any"}, 0x1},
+ {{"cs", "hs", "nlast"}, 0x2},
+ {{"cc", "lo", "ul", "last"}, 0x3},
+ {{"mi", "first"}, 0x4},
+ {{"pl", "nfrst"}, 0x5},
{{"vs"}, 0x6},
{{"vc"}, 0x7},
- {{"hi"}, 0x8},
- {{"ls"}, 0x9},
- {{"ge"}, 0xa},
- {{"lt"}, 0xb},
+ {{"hi", "pmore"}, 0x8},
+ {{"ls", "plast"}, 0x9},
+ {{"ge", "tcont"}, 0xa},
+ {{"lt", "tstop"}, 0xb},
{{"gt"}, 0xc},
{{"le"}, 0xd},
{{"al"}, 0xe},
switch (log_e)
{
case 1: imm = (imm << 2) | imm;
+ /* Fall through. */
case 2: imm = (imm << 4) | imm;
+ /* Fall through. */
case 3: imm = (imm << 8) | imm;
+ /* Fall through. */
case 4: imm = (imm << 16) | imm;
+ /* Fall through. */
case 5: imm = (imm << 32) | imm;
+ /* Fall through. */
case 6: break;
default: abort ();
}
if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
{
set_other_error (mismatch_detail, idx,
- _("shift amount expected to be 0 or 12"));
+ _("shift amount must be 0 or 12"));
return 0;
}
if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
if (!value_aligned_p (opnd->shifter.amount, 16))
{
set_other_error (mismatch_detail, idx,
- _("shift amount should be a multiple of 16"));
+ _("shift amount must be a multiple of 16"));
return 0;
}
if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
{
case OP_MOV_IMM_WIDEN:
imm = ~imm;
- /* Fall through... */
+ /* Fall through. */
case OP_MOV_IMM_WIDE:
if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
{
if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
{
set_other_error (mismatch_detail, idx,
- _("shift amount expected to be 0 or 16"));
+ _("shift amount must be 0 or 16"));
return 0;
}
break;
if (opnd->addr.writeback)
{
if (opnd->addr.preind)
- snprintf (buf, size, "[%s,#%d]!", base, opnd->addr.offset.imm);
+ snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
else
- snprintf (buf, size, "[%s],#%d", base, opnd->addr.offset.imm);
+ snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
}
else
{
if (opnd->shifter.operator_present)
{
assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
- snprintf (buf, size, "[%s,#%d,mul vl]",
+ snprintf (buf, size, "[%s, #%d, mul vl]",
base, opnd->addr.offset.imm);
}
else if (opnd->addr.offset.imm)
- snprintf (buf, size, "[%s,#%d]", base, opnd->addr.offset.imm);
+ snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
else
snprintf (buf, size, "[%s]", base);
}
if (print_extend_p)
{
if (print_amount_p)
- snprintf (tb, sizeof (tb), ",%s #%" PRIi64, shift_name,
+ snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
opnd->shifter.amount);
else
- snprintf (tb, sizeof (tb), ",%s", shift_name);
+ snprintf (tb, sizeof (tb), ", %s", shift_name);
}
else
tb[0] = '\0';
- snprintf (buf, size, "[%s,%s%s]", base, offset, tb);
+ snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
}
/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bfd_vma *address)
{
- int i;
+ unsigned int i, num_conds;
const char *name = NULL;
const aarch64_opnd_info *opnd = opnds + idx;
enum aarch64_modifier_kind kind;
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
+ case AARCH64_OPND_SVE_Rm:
/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
the <ic_op>, therefore we we use opnd->present to override the
generic optional-ness information. */
- if (opnd->type == AARCH64_OPND_Rt_SYS && !opnd->present)
- break;
+ if (opnd->type == AARCH64_OPND_Rt_SYS)
+ {
+ if (!opnd->present)
+ break;
+ }
/* Omit the operand, e.g. RET. */
- if (optional_operand_p (opcode, idx)
- && opnd->reg.regno == get_optional_operand_default_value (opcode))
+ else if (optional_operand_p (opcode, idx)
+ && (opnd->reg.regno
+ == get_optional_operand_default_value (opcode)))
break;
assert (opnd->qualifier == AARCH64_OPND_QLF_W
|| opnd->qualifier == AARCH64_OPND_QLF_X);
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
+ case AARCH64_OPND_SVE_Rn_SP:
assert (opnd->qualifier == AARCH64_OPND_QLF_W
|| opnd->qualifier == AARCH64_OPND_QLF_WSP
|| opnd->qualifier == AARCH64_OPND_QLF_X
case AARCH64_OPND_Sd:
case AARCH64_OPND_Sn:
case AARCH64_OPND_Sm:
+ case AARCH64_OPND_SVE_VZn:
+ case AARCH64_OPND_SVE_Vd:
+ case AARCH64_OPND_SVE_Vm:
+ case AARCH64_OPND_SVE_Vn:
snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
opnd->reg.regno);
break;
case AARCH64_OPND_COND:
case AARCH64_OPND_COND1:
snprintf (buf, size, "%s", opnd->cond->names[0]);
+ num_conds = ARRAY_SIZE (opnd->cond->names);
+ for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
+ {
+ size_t len = strlen (buf);
+ if (i == 1)
+ snprintf (buf + len, size - len, " // %s = %s",
+ opnd->cond->names[0], opnd->cond->names[i]);
+ else
+ snprintf (buf + len, size - len, ", %s",
+ opnd->cond->names[i]);
+ }
break;
case AARCH64_OPND_ADDR_ADRP:
case AARCH64_OPND_ADDR_UIMM12:
name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
if (opnd->addr.offset.imm)
- snprintf (buf, size, "[%s,#%d]", name, opnd->addr.offset.imm);
+ snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
else
snprintf (buf, size, "[%s]", name);
break;
projects / deliverable / binutils-gdb.git / blobdiff