AArch64: Fix error checking for SIMD udot (by element)

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index d2a4f2f97e28f5a2d22ed042f3c753ffd6c969af..44d2ca66fab7cdb2f7e432e82634eddc31b499c3 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -703,7 +703,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
   {4, 1, 0x2, "s", OQK_OPD_VARIANT},
   {8, 1, 0x3, "d", OQK_OPD_VARIANT},
   {16, 1, 0x4, "q", OQK_OPD_VARIANT},
-  {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
+  {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
 
   {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
   {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
@@ -2490,9 +2490,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
          assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
          /* MSR UAO, #uimm4
             MSR PAN, #uimm4
+            MSR SSBS,#uimm4
             The immediate must be #0 or #1.  */
          if ((opnd->pstatefield == 0x03        /* UAO.  */
               || opnd->pstatefield == 0x04     /* PAN.  */
+              || opnd->pstatefield == 0x19     /* SSBS.  */
               || opnd->pstatefield == 0x1a)    /* DIT.  */
              && opnds[1].imm.value > 1)
            {
@@ -2525,6 +2527,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
       else
        num = 16;
       num = num / aarch64_get_qualifier_esize (qualifier) - 1;
+      assert (aarch64_get_qualifier_nelem (qualifier) == 1);
 
       /* Index out-of-range.  */
       if (!value_in_range_p (opnd->reglane.index, 0, num))
@@ -3708,6 +3711,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "pan",             CPEN_(0,C2,3),  F_ARCHEXT },
   { "uao",             CPEN_ (0, C2, 4), F_ARCHEXT },
   { "nzcv",             CPEN_(3,C2,0), 0 },
+  { "ssbs",            CPEN_(3,C2,6),  F_ARCHEXT },
   { "fpcr",             CPEN_(3,C4,0), 0 },
   { "fpsr",             CPEN_(3,C4,1), 0 },
   { "dspsr_el0",        CPEN_(3,C5,0), 0 },
@@ -3733,6 +3737,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "id_dfr0_el1",      CPENC(3,0,C0,C1,2),    F_REG_READ }, /* RO */
   { "id_pfr0_el1",      CPENC(3,0,C0,C1,0),    F_REG_READ }, /* RO */
   { "id_pfr1_el1",      CPENC(3,0,C0,C1,1),    F_REG_READ }, /* RO */
+  { "id_pfr2_el1",      CPENC(3,0,C0,C3,4),    F_ARCHEXT | F_REG_READ}, /* RO */
   { "id_afr0_el1",      CPENC(3,0,C0,C1,3),    F_REG_READ }, /* RO */
   { "id_mmfr0_el1",     CPENC(3,0,C0,C1,4),    F_REG_READ }, /* RO */
   { "id_mmfr1_el1",     CPENC(3,0,C0,C1,5),    F_REG_READ }, /* RO */
@@ -3869,6 +3874,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "tpidr_el1",        CPENC(3,0,C13,C0,4),   0 },
   { "tpidr_el2",        CPENC(3,4,C13,C0,2),   0 },
   { "tpidr_el3",        CPENC(3,6,C13,C0,2),   0 },
+  { "scxtnum_el0",      CPENC(3,3,C13,C0,7), F_ARCHEXT },
+  { "scxtnum_el1",      CPENC(3,0,C13,C0,7), F_ARCHEXT },
+  { "scxtnum_el2",      CPENC(3,4,C13,C0,7), F_ARCHEXT },
+  { "scxtnum_el12",     CPENC(3,5,C13,C0,7), F_ARCHEXT },
+  { "scxtnum_el3",      CPENC(3,6,C13,C0,7), F_ARCHEXT },
   { "teecr32_el1",      CPENC(2,2,C0, C0,0),   0 }, /* See section 3.9.7.1 */
   { "cntfrq_el0",       CPENC(3,3,C14,C0,0),   0 }, /* RW */
   { "cntpct_el0",       CPENC(3,3,C14,C0,1),   F_REG_READ }, /* RO */
@@ -4108,6 +4118,25 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
     return FALSE;
 
+  /* SCXTNUM_ELx registers.  */
+  if ((reg->value == CPENC (3, 3, C13, C0, 7)
+       || reg->value == CPENC (3, 0, C13, C0, 7)
+       || reg->value == CPENC (3, 4, C13, C0, 7)
+       || reg->value == CPENC (3, 6, C13, C0, 7)
+       || reg->value == CPENC (3, 5, C13, C0, 7))
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
+      return FALSE;
+
+  /* ID_PFR2_EL1 register.  */
+  if (reg->value == CPENC(3, 0, C0, C3, 4)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
+    return FALSE;
+
+  /* SSBS.  Values are from aarch64_sys_regs.  */
+  if (reg->value == CPEN_(3,C2,6)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
+    return FALSE;
+
   /* Virtualization host extensions: system registers.  */
   if ((reg->value == CPENC (3, 4, C2, C0, 1)
        || reg->value == CPENC (3, 4, C13, C0, 1)
@@ -4320,6 +4349,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
   { "daifclr",          0x1f,  0 },
   { "pan",             0x04,   F_ARCHEXT },
   { "uao",             0x03,   F_ARCHEXT },
+  { "ssbs",            0x19,   F_ARCHEXT },
   { "dit",             0x1a,   F_ARCHEXT },
   { 0,          CPENC(0,0,0,0,0), 0 },
 };
@@ -4341,6 +4371,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
 
+  /* SSBS.  Values are from aarch64_pstatefields.  */
+  if (reg->value == 0x19
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
+    return FALSE;
+
   /* DIT.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x1a
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))