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[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index b5e0984f6c6eb527538d139cb1dda460c7b4a537..72ecf5b61e59736903f46ae01db00b5089ae6cfc 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1,5 +1,5 @@
 /* aarch64-opc.c -- AArch64 opcode support.
-   Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+   Copyright 2009, 2010, 2011, 2012, 2013  Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -334,10 +334,10 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
     { "sy",    0xf },
 };
 
-/* op -> op:       load = 0 store = 1
+/* op -> op:       load = 0 instruction = 1 store = 2
    l  -> level:    1-3
    t  -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1   */
-#define B(op,l,t) ((((op) * 2) << 3) | (((l) - 1) << 1) | (t))
+#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
 const struct aarch64_name_value_pair aarch64_prfops[32] =
 {
   { "pldl1keep", B(0, 1, 0) },
@@ -348,20 +348,20 @@ const struct aarch64_name_value_pair aarch64_prfops[32] =
   { "pldl3strm", B(0, 3, 1) },
   { "#0x06", 0x06 },
   { "#0x07", 0x07 },
-  { "#0x08", 0x08 },
-  { "#0x09", 0x09 },
-  { "#0x0a", 0x0a },
-  { "#0x0b", 0x0b },
-  { "#0x0c", 0x0c },
-  { "#0x0d", 0x0d },
+  { "plil1keep", B(1, 1, 0) },
+  { "plil1strm", B(1, 1, 1) },
+  { "plil2keep", B(1, 2, 0) },
+  { "plil2strm", B(1, 2, 1) },
+  { "plil3keep", B(1, 3, 0) },
+  { "plil3strm", B(1, 3, 1) },
   { "#0x0e", 0x0e },
   { "#0x0f", 0x0f },
-  { "pstl1keep", B(1, 1, 0) },
-  { "pstl1strm", B(1, 1, 1) },
-  { "pstl2keep", B(1, 2, 0) },
-  { "pstl2strm", B(1, 2, 1) },
-  { "pstl3keep", B(1, 3, 0) },
-  { "pstl3strm", B(1, 3, 1) },
+  { "pstl1keep", B(2, 1, 0) },
+  { "pstl1strm", B(2, 1, 1) },
+  { "pstl2keep", B(2, 2, 0) },
+  { "pstl2strm", B(2, 2, 1) },
+  { "pstl3keep", B(2, 3, 0) },
+  { "pstl3strm", B(2, 3, 1) },
   { "#0x16", 0x16 },
   { "#0x17", 0x17 },
   { "#0x18", 0x18 },
@@ -2433,10 +2433,26 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_IMMR:
     case AARCH64_OPND_IMMS:
     case AARCH64_OPND_FBITS:
-    case AARCH64_OPND_IMM_MOV:
       snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       break;
 
+    case AARCH64_OPND_IMM_MOV:
+      switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
+       {
+       case 4: /* e.g. MOV Wd, #<imm32>.  */
+           {
+             int imm32 = opnd->imm.value;
+             snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
+           }
+         break;
+       case 8: /* e.g. MOV Xd, #<imm64>.  */
+         snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
+                   opnd->imm.value, opnd->imm.value);
+         break;
+       default: assert (0);
+       }
+      break;
+
     case AARCH64_OPND_FPIMM0:
       snprintf (buf, size, "#0.0");
       break;