[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 2ae2f1047ec09628cadece9cdb8aad5fad8d701a..86aeae004f890c43eb745876bb9d94d404fe3ac5 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3264,6 +3264,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
     { "cvac",       CPENS (3, C7, C10, 1), F_HASXT },
     { "csw",       CPENS (0, C7, C10, 2), F_HASXT },
     { "cvau",       CPENS (3, C7, C11, 1), F_HASXT },
+    { "cvap",       CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
     { "civac",      CPENS (3, C7, C14, 1), F_HASXT },
     { "cisw",       CPENS (0, C7, C14, 2), F_HASXT },
     { 0,       CPENS(0,0,0,0), 0 }
@@ -3329,6 +3330,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
   return (sys_ins_reg->flags & F_HASXT) != 0;
 }
 
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
+                                const aarch64_sys_ins_reg *reg)
+{
+  if (!(reg->flags & F_ARCHEXT))
+    return TRUE;
+
+  /* DC CVAP.  Values are from aarch64_sys_regs_dc.  */
+  if (reg->value == CPENS (3, C7, C12, 1)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+    return FALSE;
+
+  return TRUE;
+}
+
 #undef C0
 #undef C1
 #undef C2