[AArch64] Add ARMv8.3 pointer authentication key registers

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index d22e419e421e7f2342ebeb62c9506a024e38248f..8e89b5b22ccb332e730560ae7d938dc6af761c39 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -334,18 +334,18 @@ aarch64_get_operand_desc (enum aarch64_opnd type)
 /* Table of all conditional affixes.  */
 const aarch64_cond aarch64_conds[16] =
 {
-  {{"eq"}, 0x0},
-  {{"ne"}, 0x1},
-  {{"cs", "hs"}, 0x2},
-  {{"cc", "lo", "ul"}, 0x3},
-  {{"mi"}, 0x4},
-  {{"pl"}, 0x5},
+  {{"eq", "none"}, 0x0},
+  {{"ne", "any"}, 0x1},
+  {{"cs", "hs", "nlast"}, 0x2},
+  {{"cc", "lo", "ul", "last"}, 0x3},
+  {{"mi", "first"}, 0x4},
+  {{"pl", "nfrst"}, 0x5},
   {{"vs"}, 0x6},
   {{"vc"}, 0x7},
-  {{"hi"}, 0x8},
-  {{"ls"}, 0x9},
-  {{"ge"}, 0xa},
-  {{"lt"}, 0xb},
+  {{"hi", "pmore"}, 0x8},
+  {{"ls", "plast"}, 0x9},
+  {{"ge", "tcont"}, 0xa},
+  {{"lt", "tstop"}, 0xb},
   {{"gt"}, 0xc},
   {{"le"}, 0xd},
   {{"al"}, 0xe},
@@ -1156,10 +1156,15 @@ build_immediate_table (void)
            switch (log_e)
              {
              case 1: imm = (imm <<  2) | imm;
+               /* Fall through.  */
              case 2: imm = (imm <<  4) | imm;
+               /* Fall through.  */
              case 3: imm = (imm <<  8) | imm;
+               /* Fall through.  */
              case 4: imm = (imm << 16) | imm;
+               /* Fall through.  */
              case 5: imm = (imm << 32) | imm;
+               /* Fall through.  */
              case 6: break;
              default: abort ();
              }
@@ -1914,7 +1919,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
          if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
            {
              set_other_error (mismatch_detail, idx,
-                              _("shift amount expected to be 0 or 12"));
+                              _("shift amount must be 0 or 12"));
              return 0;
            }
          if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
@@ -1937,7 +1942,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
          if (!value_aligned_p (opnd->shifter.amount, 16))
            {
              set_other_error (mismatch_detail, idx,
-                              _("shift amount should be a multiple of 16"));
+                              _("shift amount must be a multiple of 16"));
              return 0;
            }
          if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
@@ -1969,7 +1974,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
                {
                case OP_MOV_IMM_WIDEN:
                  imm = ~imm;
-                 /* Fall through...  */
+                 /* Fall through.  */
                case OP_MOV_IMM_WIDE:
                  if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
                    {
@@ -2174,7 +2179,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
              if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
                {
                  set_other_error (mismatch_detail, idx,
-                                  _("shift amount expected to be 0 or 16"));
+                                  _("shift amount must be 0 or 16"));
                  return 0;
                }
              break;
@@ -2864,20 +2869,20 @@ print_immediate_offset_address (char *buf, size_t size,
   if (opnd->addr.writeback)
     {
       if (opnd->addr.preind)
-       snprintf (buf, size, "[%s,#%d]!", base, opnd->addr.offset.imm);
+       snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
       else
-       snprintf (buf, size, "[%s],#%d", base, opnd->addr.offset.imm);
+       snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
     }
   else
     {
       if (opnd->shifter.operator_present)
        {
          assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
-         snprintf (buf, size, "[%s,#%d,mul vl]",
+         snprintf (buf, size, "[%s, #%d, mul vl]",
                    base, opnd->addr.offset.imm);
        }
       else if (opnd->addr.offset.imm)
-       snprintf (buf, size, "[%s,#%d]", base, opnd->addr.offset.imm);
+       snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
       else
        snprintf (buf, size, "[%s]", base);
     }
@@ -2912,15 +2917,15 @@ print_register_offset_address (char *buf, size_t size,
   if (print_extend_p)
     {
       if (print_amount_p)
-       snprintf (tb, sizeof (tb), ",%s #%" PRIi64, shift_name,
+       snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
                  opnd->shifter.amount);
       else
-       snprintf (tb, sizeof (tb), ",%s", shift_name);
+       snprintf (tb, sizeof (tb), ", %s", shift_name);
     }
   else
     tb[0] = '\0';
 
-  snprintf (buf, size, "[%s,%s%s]", base, offset, tb);
+  snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
 }
 
 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
@@ -2940,7 +2945,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
                       const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
                       bfd_vma *address)
 {
-  int i;
+  unsigned int i, num_conds;
   const char *name = NULL;
   const aarch64_opnd_info *opnd = opnds + idx;
   enum aarch64_modifier_kind kind;
@@ -2965,11 +2970,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
       /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
         the <ic_op>, therefore we we use opnd->present to override the
         generic optional-ness information.  */
-      if (opnd->type == AARCH64_OPND_Rt_SYS && !opnd->present)
-       break;
+      if (opnd->type == AARCH64_OPND_Rt_SYS)
+       {
+         if (!opnd->present)
+           break;
+       }
       /* Omit the operand, e.g. RET.  */
-      if (optional_operand_p (opcode, idx)
-         && opnd->reg.regno == get_optional_operand_default_value (opcode))
+      else if (optional_operand_p (opcode, idx)
+              && (opnd->reg.regno
+                  == get_optional_operand_default_value (opcode)))
        break;
       assert (opnd->qualifier == AARCH64_OPND_QLF_W
              || opnd->qualifier == AARCH64_OPND_QLF_X);
@@ -3306,6 +3315,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_COND:
     case AARCH64_OPND_COND1:
       snprintf (buf, size, "%s", opnd->cond->names[0]);
+      num_conds = ARRAY_SIZE (opnd->cond->names);
+      for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
+       {
+         size_t len = strlen (buf);
+         if (i == 1)
+           snprintf (buf + len, size - len, "  // %s = %s",
+                     opnd->cond->names[0], opnd->cond->names[i]);
+         else
+           snprintf (buf + len, size - len, ", %s",
+                     opnd->cond->names[i]);
+       }
       break;
 
     case AARCH64_OPND_ADDR_ADRP:
@@ -3422,7 +3442,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_ADDR_UIMM12:
       name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
       if (opnd->addr.offset.imm)
-       snprintf (buf, size, "[%s,#%d]", name, opnd->addr.offset.imm);
+       snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
       else
        snprintf (buf, size, "[%s]", name);
       break;
@@ -3630,6 +3650,16 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "tcr_el3",          CPENC(3,6,C2,C0,2),    0 },
   { "tcr_el12",                CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
   { "vtcr_el2",         CPENC(3,4,C2,C1,2),    0 },
+  { "apiakeylo_el1",   CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
+  { "apiakeyhi_el1",   CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
+  { "apibkeylo_el1",   CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
+  { "apibkeyhi_el1",   CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
+  { "apdakeylo_el1",   CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
+  { "apdakeyhi_el1",   CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
+  { "apdbkeylo_el1",   CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
+  { "apdbkeyhi_el1",   CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
+  { "apgakeylo_el1",   CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
+  { "apgakeyhi_el1",   CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
   { "afsr0_el1",        CPENC(3,0,C5,C1,0),    0 },
   { "afsr1_el1",        CPENC(3,0,C5,C1,1),    0 },
   { "afsr0_el2",        CPENC(3,4,C5,C1,0),    0 },
@@ -4006,6 +4036,20 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
     return FALSE;
 
+  /* ARMv8.3 Pointer authentication keys.  */
+  if ((reg->value == CPENC (3, 0, C2, C1, 0)
+       || reg->value == CPENC (3, 0, C2, C1, 1)
+       || reg->value == CPENC (3, 0, C2, C1, 2)
+       || reg->value == CPENC (3, 0, C2, C1, 3)
+       || reg->value == CPENC (3, 0, C2, C2, 0)
+       || reg->value == CPENC (3, 0, C2, C2, 1)
+       || reg->value == CPENC (3, 0, C2, C2, 2)
+       || reg->value == CPENC (3, 0, C2, C2, 3)
+       || reg->value == CPENC (3, 0, C2, C3, 0)
+       || reg->value == CPENC (3, 0, C2, C3, 1))
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
+    return FALSE;
+
   return TRUE;
 }