Add support for RISC-V architecture.

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.h

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index e823146275531581932f40f0da35a7ee4bb942f6..91c78f433e9a55930fabae4e43289a41294fbb02 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -91,6 +91,10 @@ enum aarch64_field_kind
   FLD_b5,
   FLD_b40,
   FLD_scale,
+  FLD_SVE_M_4,
+  FLD_SVE_M_14,
+  FLD_SVE_M_16,
+  FLD_SVE_N,
   FLD_SVE_Pd,
   FLD_SVE_Pg3,
   FLD_SVE_Pg4_5,
@@ -99,6 +103,11 @@ enum aarch64_field_kind
   FLD_SVE_Pm,
   FLD_SVE_Pn,
   FLD_SVE_Pt,
+  FLD_SVE_Rm,
+  FLD_SVE_Rn,
+  FLD_SVE_Vd,
+  FLD_SVE_Vm,
+  FLD_SVE_Vn,
   FLD_SVE_Za_5,
   FLD_SVE_Za_16,
   FLD_SVE_Zd,
@@ -106,12 +115,25 @@ enum aarch64_field_kind
   FLD_SVE_Zm_16,
   FLD_SVE_Zn,
   FLD_SVE_Zt,
+  FLD_SVE_i1,
+  FLD_SVE_imm3,
   FLD_SVE_imm4,
+  FLD_SVE_imm5,
+  FLD_SVE_imm5b,
   FLD_SVE_imm6,
+  FLD_SVE_imm7,
+  FLD_SVE_imm8,
+  FLD_SVE_imm9,
+  FLD_SVE_immr,
+  FLD_SVE_imms,
   FLD_SVE_msz,
   FLD_SVE_pattern,
   FLD_SVE_prfop,
+  FLD_SVE_sz,
+  FLD_SVE_tsz,
   FLD_SVE_tszh,
+  FLD_SVE_tszl_8,
+  FLD_SVE_tszl_19,
   FLD_SVE_xs_14,
   FLD_SVE_xs_22,
 };
@@ -311,6 +333,9 @@ extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 {
   return extract_field_2 (&fields[kind], code, mask);
 }
+
+extern aarch64_insn
+extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 \f
 /* Inline functions selecting operand to do the encoding/decoding for a
    certain instruction bit-field.  */