QLF4(X,X,imm_0_63,imm_0_63), \
}
+/* e.g. BFC <Wd>, #<immr>, #<imms>. */
+#define QL_BF1 \
+{ \
+ QLF3 (W, imm_0_31, imm_1_32), \
+ QLF3 (X, imm_0_63, imm_1_64), \
+}
+
/* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */
#define QL_BF2 \
{ \
QLF3(S_S,X,imm_1_64), \
}
+/* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */
+#define QL_FIX2FP_H \
+{ \
+ QLF3 (S_H, W, imm_1_32), \
+ QLF3 (S_H, X, imm_1_64), \
+}
+
/* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */
#define QL_FP2FIX \
{ \
QLF3(X,S_S,imm_1_64), \
}
+/* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */
+#define QL_FP2FIX_H \
+{ \
+ QLF3 (W, S_H, imm_1_32), \
+ QLF3 (X, S_H, imm_1_64), \
+}
+
/* e.g. SCVTF <Dd>, <Wn>. */
#define QL_INT2FP \
{ \
QLF2(S_S,X), \
}
+/* e.g. SCVTF <Hd>, <Wn>. */
+#define QL_INT2FP_H \
+{ \
+ QLF2 (S_H, W), \
+ QLF2 (S_H, X), \
+}
+
/* e.g. FCVTNS <Xd>, <Dn>. */
#define QL_FP2INT \
{ \
QLF2(X,S_S), \
}
+/* e.g. FCVTNS <Hd>, <Wn>. */
+#define QL_FP2INT_H \
+{ \
+ QLF2 (W, S_H), \
+ QLF2 (X, S_H), \
+}
+
/* e.g. FMOV <Xd>, <Vn>.D[1]. */
#define QL_XVD1 \
{ \
QLF2(S_D, S_D), \
}
+/* FMOV <Hd>, <Hn>. */
+#define QL_FP2_H \
+{ \
+ QLF2 (S_H, S_H), \
+}
+
/* e.g. SQADD <V><d>, <V><n>, <V><m>. */
#define QL_S_3SAME \
{ \
QLF3(S_D, S_D, S_D), \
}
+/* FMUL <Hd>, <Hn>, <Hm>. */
+#define QL_FP3_H \
+{ \
+ QLF3 (S_H, S_H, S_H), \
+}
+
/* FMADD <Dd>, <Dn>, <Dm>, <Da>. */
#define QL_FP4 \
{ \
QLF4(S_D, S_D, S_D, S_D), \
}
+/* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */
+#define QL_FP4_H \
+{ \
+ QLF4 (S_H, S_H, S_H, S_H), \
+}
+
/* e.g. FCMP <Dn>, #0.0. */
#define QL_DST_SD \
{ \
QLF2(S_D, NIL), \
}
+/* e.g. FCMP <Hn>, #0.0. */
+#define QL_DST_H \
+{ \
+ QLF2 (S_H, NIL), \
+}
+
/* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */
#define QL_FP_COND \
{ \
QLF4(S_D, S_D, S_D, NIL), \
}
+/* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */
+#define QL_FP_COND_H \
+{ \
+ QLF4 (S_H, S_H, S_H, NIL), \
+}
+
/* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */
#define QL_CCMP \
{ \
QLF4(S_D, S_D, NIL, NIL), \
}
+/* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
+#define QL_FCCMP_H \
+{ \
+ QLF4 (S_H, S_H, NIL, NIL), \
+}
+
/* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */
#define QL_DUP_VX \
{ \
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
+static const aarch64_feature_set aarch64_feature_lor =
+ AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
+static const aarch64_feature_set aarch64_feature_rdma =
+ AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
+static const aarch64_feature_set aarch64_feature_v8_2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
+static const aarch64_feature_set aarch64_feature_fp_f16 =
+ AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
#define CRYPTO &aarch64_feature_crypto
#define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse
+#define LOR &aarch64_feature_lor
+#define RDMA &aarch64_feature_rdma
+#define FP_F16 &aarch64_feature_fp_f16
+#define ARMV8_2 &aarch64_feature_v8_2
struct aarch64_opcode aarch64_opcode_table[] =
{
{"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
{"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
{"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
+ {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
/* AdvSIMD EXT. */
- {"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
+ {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
/* AdvSIMD modified immediate. */
{"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
{"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
{"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
{"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
{"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ /* AdvSIMD three same extension. */
+ {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
+ {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
/* AdvSIMD shift by immediate. */
{"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
{"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
{"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+ {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
+ {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
/* AdvSIMD load/store multiple structures. */
{"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
{"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
{"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
{"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
{"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ /* AdvSIMDs scalar three same extension. */
+ {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
+ {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
/* AdvSIMD scalar shift by immediate. */
{"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
{"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
{"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
+ {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2,
+ OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV},
{"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
{"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
{"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
{"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0},
- {"rev", 0xdac00c00, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
+ {"rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, CORE,
+ OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1},
+ {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2,
+ OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS},
{"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
{"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV},
/* Floating-point<->fixed-point conversions. */
{"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
+ {"scvtf", 0x1ec20000, 0x7f3f0000, float2fix, 0, FP_F16,
+ OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
{"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
+ {"ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, 0, FP_F16,
+ OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
{"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
+ {"fcvtzs", 0x1ed80000, 0x7f3f0000, float2fix, 0, FP_F16,
+ OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
{"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
+ {"fcvtzu", 0x1ed90000, 0x7f3f0000, float2fix, 0, FP_F16,
+ OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
/* Floating-point<->integer conversions. */
{"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtns", 0x1ee00000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtnu", 0x1ee10000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+ {"scvtf", 0x1ee20000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
{"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+ {"ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
{"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtas", 0x1ee40000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtau", 0x1ee50000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fmov", 0x1ee60000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+ {"fmov", 0x1ee70000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
{"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtps", 0x1ee80000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtpu", 0x1ee90000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtms", 0x1ef00000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtmu", 0x1ef10000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtzs", 0x1ef80000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
+ {"fcvtzu", 0x1ef90000, 0x7f3ffc00, float2int, 0, FP_F16,
+ OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
{"fmov", 0x9eae0000, 0xfffffc00, float2int, 0, FP, OP2 (Rd, VnD1), QL_XVD1, 0},
{"fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, FP, OP2 (VdD1, Rn), QL_VD1X, 0},
/* Floating-point conditional compare. */
{"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
+ {"fccmp", 0x1ee00400, 0xff200c10, floatccmp, 0, FP_F16,
+ OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
{"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
+ {"fccmpe", 0x1ee00410, 0xff200c10, floatccmp, 0, FP_F16,
+ OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
/* Floating-point compare. */
{"fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
+ {"fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, 0, FP_F16,
+ OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
{"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
+ {"fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, 0, FP_F16,
+ OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
{"fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
+ {"fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, 0, FP_F16,
+ OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
{"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
+ {"fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, 0, FP_F16,
+ OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
/* Floating-point data-processing (1 source). */
{"fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fmov", 0x1ee04000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fneg", 0x1ee14000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC},
{"frintn", 0x1e244000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintn", 0x1ee44000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"frintp", 0x1e24c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintp", 0x1ee4c000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"frintm", 0x1e254000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintm", 0x1ee54000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"frintz", 0x1e25c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintz", 0x1ee5c000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"frinta", 0x1e264000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frinta", 0x1ee64000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"frintx", 0x1e274000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frintx", 0x1ee74000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
{"frinti", 0x1e27c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
+ {"frinti", 0x1ee7c000, 0xff3ffc00, floatdp1, 0, FP_F16,
+ OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
/* Floating-point data-processing (2 source). */
{"fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmul", 0x1ee00800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fdiv", 0x1ee01800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fadd", 0x1ee02800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fsub", 0x1ee03800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmax", 0x1ee04800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmin", 0x1ee05800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fmaxnm", 0x1ee06800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fminnm", 0x1e207800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fminnm", 0x1ee07800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
{"fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
+ {"fnmul", 0x1ee08800, 0xff20fc00, floatdp2, 0, FP_F16,
+ OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
/* Floating-point data-processing (3 source). */
{"fmadd", 0x1f000000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fmadd", 0x1fc00000, 0xff208000, floatdp3, 0, FP_F16,
+ OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
{"fmsub", 0x1f008000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fmsub", 0x1fc08000, 0xff208000, floatdp3, 0, FP_F16,
+ OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
{"fnmadd", 0x1f200000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fnmadd", 0x1fe00000, 0xff208000, floatdp3, 0, FP_F16,
+ OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
{"fnmsub", 0x1f208000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
+ {"fnmsub", 0x1fe08000, 0xff208000, floatdp3, 0, FP_F16,
+ OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
/* Floating-point immediate. */
{"fmov", 0x1e201000, 0xff201fe0, floatimm, 0, FP, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE},
+ {"fmov", 0x1ee01000, 0xff201fe0, floatimm, 0, FP_F16,
+ OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE},
/* Floating-point conditional select. */
{"fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, FP, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE},
+ {"fcsel", 0x1ee00c00, 0xff200c00, floatsel, 0, FP_F16,
+ OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE},
/* Load/store register (immediate indexed). */
{"strb", 0x38000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
{"ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
{"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
{"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
{"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ /* Limited Ordering Regions load/store instructions. */
+ {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
/* Load/store no-allocate pair (offset). */
{"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
{"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
projects / deliverable / binutils-gdb.git / blobdiff