/* alpha-opc.c -- Alpha AXP opcode list
- Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+ Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@cygnus.com>,
patterned after the PPC opcode handling written by Ian Lance Taylor.
the RA field into the RB field, and the extraction function just
checks that the fields are the same. */
-/*ARGSUSED*/
static unsigned
insert_rba(insn, value, errmsg)
unsigned insn;
/* The same for the RC field */
-/*ARGSUSED*/
static unsigned
insert_rca(insn, value, errmsg)
unsigned insn;
/* Fake arguments in which the registers must be set to ZERO */
-/*ARGSUSED*/
static unsigned
insert_za(insn, value, errmsg)
unsigned insn;
return 0;
}
-/*ARGSUSED*/
static unsigned
insert_zb(insn, value, errmsg)
unsigned insn;
return 0;
}
-/*ARGSUSED*/
static unsigned
insert_zc(insn, value, errmsg)
unsigned insn;
return insn | ((value / 4) & 0x1FFFFF);
}
-/*ARGSUSED*/
static int
extract_bdisp(insn, invalid)
unsigned insn;
return insn | ((value / 4) & 0x3FFF);
}
-/*ARGSUSED*/
static int
extract_jhint(insn, invalid)
unsigned insn;
return insn | ((value / 4) & 0x1FFF);
}
-/*ARGSUSED*/
static int
extract_ev6hwjhint(insn, invalid)
unsigned insn;
{ "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
{ "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
{ "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
+ { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
{ "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
{ "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
{ "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
+ { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE },
+ { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE },
+ { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE },
{ "call_pal", PCD(0x00), BASE, ARG_PCD },
{ "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */
{ "wmb", MFC(0x18,0x4400), BASE, ARG_NONE },
{ "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
{ "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
- { "rpcc", MFC(0x18,0xC000), BASE, { RA } },
+ { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } },
+ { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */
{ "rc", MFC(0x18,0xE000), BASE, { RA } },
{ "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
{ "rs", MFC(0x18,0xF000), BASE, { RA } },