fixed braino in changelog entry for replacement of "switches" with "options"

[deliverable/binutils-gdb.git] / opcodes / alpha-opc.c

diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c
index 7680f47d2a180db2884db4591c6090eff3a5750d..7a20a55d95cc3c30d351a4ccd6f1c0954e47b6db 100644 (file)
--- a/opcodes/alpha-opc.c
+++ b/opcodes/alpha-opc.c
@@ -30,10 +30,10 @@
    almost all of the extended instruction mnemonics.  This permits the
    disassembler to use them, and simplifies the assembler logic, at the
    cost of increasing the table size.  The table is strictly constant
-   data, so the compiler should be able to put it in the .text section.
+   data, so the compiler should be able to put it in the text segment.
 
    This file also holds the operand table.  All knowledge about inserting
-   operands into instructions and vice-versa is kept in this file.
+   and extracting operands from instructions is kept in this file.
 
    The information for the base instruction set was compiled from the
    _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
@@ -542,7 +542,8 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "lda",             MEM(0x08), BASE, ARG_MEM },
   { "ldah",            MEM(0x09), BASE, ARG_MEM },
   { "ldbu",            MEM(0x0A), BWX, ARG_MEM },
-  { "unop",            MEM(0x0B), BASE, { ZA } },              /* pseudo */
+  { "unop",            MEM_(0x0B) | (30 << 16),
+                       MEM_MASK, BASE, { ZA } },               /* pseudo */
   { "ldq_u",           MEM(0x0B), BASE, ARG_MEM },
   { "ldwu",            MEM(0x0C), BWX, ARG_MEM },
   { "stw",             MEM(0x0D), BWX, ARG_MEM },
@@ -1103,6 +1104,7 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "ecb",             MFC(0x18,0xE800), BASE, { ZA, PRB } },  /* ev56 una */
   { "rs",              MFC(0x18,0xF000), BASE, { RA } },
   { "wh64",            MFC(0x18,0xF800), BASE, { ZA, PRB } },  /* ev56 una */
+  { "wh64en",          MFC(0x18,0xFC00), BASE, { ZA, PRB } },  /* ev7 una */
 
   { "hw_mfpr",         OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
   { "hw_mfpr",         OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },