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[deliverable/binutils-gdb.git] / opcodes / alpha-opc.c

diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c
index d5f0314449ebaf6f97a43285e95881370916c8cb..f342e788cc6ea13304179025de1bd489f35c3e90 100644 (file)
--- a/opcodes/alpha-opc.c
+++ b/opcodes/alpha-opc.c
@@ -1,5 +1,6 @@
 /* alpha-opc.c -- Alpha AXP opcode list
-   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Free Software Foundation, Inc.
    Contributed by Richard Henderson <rth@cygnus.com>,
    patterned after the PPC opcode handling written by Ian Lance Taylor.
 
@@ -17,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this file; see the file COPYING.  If not, write to the
-   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "sysdep.h"
@@ -214,7 +215,6 @@ const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operand
    the RA field into the RB field, and the extraction function just
    checks that the fields are the same. */
 
-/*ARGSUSED*/
 static unsigned
 insert_rba(insn, value, errmsg)
      unsigned insn;
@@ -238,7 +238,6 @@ extract_rba(insn, invalid)
 
 /* The same for the RC field */
 
-/*ARGSUSED*/
 static unsigned
 insert_rca(insn, value, errmsg)
      unsigned insn;
@@ -262,7 +261,6 @@ extract_rca(insn, invalid)
 
 /* Fake arguments in which the registers must be set to ZERO */
 
-/*ARGSUSED*/
 static unsigned
 insert_za(insn, value, errmsg)
      unsigned insn;
@@ -282,7 +280,6 @@ extract_za(insn, invalid)
   return 0;
 }
 
-/*ARGSUSED*/
 static unsigned
 insert_zb(insn, value, errmsg)
      unsigned insn;
@@ -302,7 +299,6 @@ extract_zb(insn, invalid)
   return 0;
 }
 
-/*ARGSUSED*/
 static unsigned
 insert_zc(insn, value, errmsg)
      unsigned insn;
@@ -336,7 +332,6 @@ insert_bdisp(insn, value, errmsg)
   return insn | ((value / 4) & 0x1FFFFF);
 }
 
-/*ARGSUSED*/
 static int
 extract_bdisp(insn, invalid)
      unsigned insn;
@@ -359,7 +354,6 @@ insert_jhint(insn, value, errmsg)
   return insn | ((value / 4) & 0x3FFF);
 }
 
-/*ARGSUSED*/
 static int
 extract_jhint(insn, invalid)
      unsigned insn;
@@ -381,7 +375,6 @@ insert_ev6hwjhint(insn, value, errmsg)
   return insn | ((value / 4) & 0x1FFF);
 }
 
-/*ARGSUSED*/
 static int
 extract_ev6hwjhint(insn, invalid)
      unsigned insn;
@@ -533,16 +526,23 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "halt",            SPCD(0x00,0x0000), BASE, ARG_NONE },
   { "draina",          SPCD(0x00,0x0002), BASE, ARG_NONE },
   { "bpt",             SPCD(0x00,0x0080), BASE, ARG_NONE },
+  { "bugchk",          SPCD(0x00,0x0081), BASE, ARG_NONE },
   { "callsys",         SPCD(0x00,0x0083), BASE, ARG_NONE },
   { "chmk",            SPCD(0x00,0x0083), BASE, ARG_NONE },
   { "imb",             SPCD(0x00,0x0086), BASE, ARG_NONE },
+  { "rduniq",          SPCD(0x00,0x009e), BASE, ARG_NONE },
+  { "wruniq",          SPCD(0x00,0x009f), BASE, ARG_NONE },
+  { "gentrap",         SPCD(0x00,0x00aa), BASE, ARG_NONE },
   { "call_pal",                PCD(0x00), BASE, ARG_PCD },
   { "pal",             PCD(0x00), BASE, ARG_PCD },             /* alias */
 
+  { "lda",             MEM(0x08), BASE, { RA, MDISP, ZB } },   /* pseudo */
   { "lda",             MEM(0x08), BASE, ARG_MEM },
+  { "ldah",            MEM(0x09), BASE, { RA, MDISP, ZB } },   /* pseudo */
   { "ldah",            MEM(0x09), BASE, ARG_MEM },
   { "ldbu",            MEM(0x0A), BWX, ARG_MEM },
-  { "unop",            MEM(0x0B), BASE, { ZA } },              /* pseudo */
+  { "unop",            MEM_(0x0B) | (30 << 16),
+                       MEM_MASK, BASE, { ZA } },               /* pseudo */
   { "ldq_u",           MEM(0x0B), BASE, ARG_MEM },
   { "ldwu",            MEM(0x0C), BWX, ARG_MEM },
   { "stw",             MEM(0x0D), BWX, ARG_MEM },
@@ -1098,7 +1098,8 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "wmb",             MFC(0x18,0x4400), BASE, ARG_NONE },
   { "fetch",           MFC(0x18,0x8000), BASE, { ZA, PRB } },
   { "fetch_m",         MFC(0x18,0xA000), BASE, { ZA, PRB } },
-  { "rpcc",            MFC(0x18,0xC000), BASE, { RA } },
+  { "rpcc",            MFC(0x18,0xC000), BASE, { RA, ZB } },
+  { "rpcc",            MFC(0x18,0xC000), BASE, { RA, RB } },   /* ev6 una */
   { "rc",              MFC(0x18,0xE000), BASE, { RA } },
   { "ecb",             MFC(0x18,0xE800), BASE, { ZA, PRB } },  /* ev56 una */
   { "rs",              MFC(0x18,0xF000), BASE, { RA } },
@@ -1117,8 +1118,12 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "hw_mfpr/pai",     OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
   { "pal19",           PCD(0x19), BASE, ARG_PCD },
 
+  { "jmp",             MBR_(0x1A,0), MBR_MASK | 0x3FFF,        /* pseudo */
+                       BASE, { ZA, CPRB } },
   { "jmp",             MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
   { "jsr",             MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
+  { "ret",             MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
+                       0xFFFFFFFF, BASE, { 0 } },
   { "ret",             MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
   { "jcr",             MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
   { "jsr_coroutine",   MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },