/* Opcode table for the ARC.
- Copyright 1994 Free Software Foundation, Inc.
+ Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This program is free software; you can redistribute it and/or modify
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+#include <stdio.h>
#include "ansidecl.h"
#include "opcode/arc.h"
+#include "opintl.h"
+
+#ifndef NULL
+#define NULL 0
+#endif
#define INSERT_FN(fn) \
static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
INSERT_FN (insert_cond);
INSERT_FN (insert_forcelimm);
INSERT_FN (insert_reladdr);
+INSERT_FN (insert_absaddr);
INSERT_FN (insert_unopmacro);
-INSERT_FN (insert_multshift);
EXTRACT_FN (extract_reg);
EXTRACT_FN (extract_flag);
EXTRACT_FN (extract_cond);
+EXTRACT_FN (extract_reladdr);
EXTRACT_FN (extract_unopmacro);
-EXTRACT_FN (extract_multshift);
/* Various types of ARC operands, including insn suffixes. */
'n' DELAY N field (nullify field)
'q' COND condition code field
'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
- 'B' BRANCH branch address
+ 'B' BRANCH branch address (22 bit pc relative)
+ 'J' JUMP jump address (26 bit absolute)
'z' SIZE1 size field in ld a,[b,c]
'Z' SIZE10 size field in ld a,[b,shimm]
'y' SIZE22 size field in st c,[b,shimm]
'x' SIGN0 sign extend field ld a,[b,c]
'X' SIGN9 sign extend field ld a,[b,shimm]
- 'u' ADDRESS3 update field in ld a,[b,c]
- 'v' ADDRESS12 update field in ld a,[b,shimm]
- 'w' ADDRESS24 update field in st c,[b,shimm]
- 'D' CACHEBYPASS5 direct to memory enable (cache bypass) in ld a,[b,c]
- 'e' CACHEBYPASS14 direct to memory enable (cache bypass) in ld a,[b,shimm]
- 'E' CACHEBYPASS26 direct to memory enable (cache bypass) in st c,[b,shimm]
+ 'w' ADDRESS3 write-back field in ld a,[b,c]
+ 'W' ADDRESS12 write-back field in ld a,[b,shimm]
+ 'v' ADDRESS24 write-back field in st c,[b,shimm]
+ 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
+ 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
+ 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
- 'M' MULTSHIFT fake operand to check if target has multiply/shifter
The following modifiers may appear between the % and char (eg: %.f):
/* register A or shimm/limm indicator */
#define REGA (UNUSED + 1)
- { 'a', 6, ARC_SHIFT_REGA, 0, insert_reg, extract_reg },
+ { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
/* register B or shimm/limm indicator */
#define REGB (REGA + 1)
- { 'b', 6, ARC_SHIFT_REGB, 0, insert_reg, extract_reg },
+ { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
/* register C or shimm/limm indicator */
#define REGC (REGB + 1)
- { 'c', 6, ARC_SHIFT_REGC, 0, insert_reg, extract_reg },
+ { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
/* fake operand used to insert shimm value into most instructions */
#define SHIMMFINISH (REGC + 1)
{ 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
-/* fake operand used to insert limm value into most instructions */
+/* fake operand used to insert limm value into most instructions. */
#define LIMMFINISH (SHIMMFINISH + 1)
- { 'L', 32, 32, ARC_OPERAND_ABSOLUTE + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
+ { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
/* shimm operand when there is no reg indicator (ld,st) */
#define SHIMMOFFSET (LIMMFINISH + 1)
#define FORCELIMM (COND + 1)
{ 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
-/* branch address b, bl, and lp insns */
+/* branch address; b, bl, and lp insns */
#define BRANCH (FORCELIMM + 1)
- { 'B', 20, 7, ARC_OPERAND_RELATIVE + ARC_OPERAND_SIGNED, insert_reladdr },
+ { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
+
+/* jump address; j insn (this is basically the same as 'L' except that the
+ value is right shifted by 2) */
+#define JUMP (BRANCH + 1)
+ { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
/* size field, stored in bit 1,2 */
-#define SIZE1 (BRANCH + 1)
+#define SIZE1 (JUMP + 1)
{ 'z', 2, 1, ARC_OPERAND_SUFFIX },
/* size field, stored in bit 10,11 */
/* address write back, stored in bit 3 */
#define ADDRESS3 (SIGN9 + 1)
- { 'u', 1, 3, ARC_OPERAND_SUFFIX },
+ { 'w', 1, 3, ARC_OPERAND_SUFFIX },
/* address write back, stored in bit 12 */
#define ADDRESS12 (ADDRESS3 + 1)
- { 'v', 1, 12, ARC_OPERAND_SUFFIX },
+ { 'W', 1, 12, ARC_OPERAND_SUFFIX },
/* address write back, stored in bit 24 */
#define ADDRESS24 (ADDRESS12 + 1)
- { 'w', 1, 24, ARC_OPERAND_SUFFIX },
+ { 'v', 1, 24, ARC_OPERAND_SUFFIX },
-/* address write back, stored in bit 3 */
+/* cache bypass, stored in bit 5 */
#define CACHEBYPASS5 (ADDRESS24 + 1)
- { 'D', 1, 5, ARC_OPERAND_SUFFIX },
+ { 'e', 1, 5, ARC_OPERAND_SUFFIX },
-/* address write back, stored in bit 12 */
+/* cache bypass, stored in bit 14 */
#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
- { 'e', 1, 14, ARC_OPERAND_SUFFIX },
+ { 'E', 1, 14, ARC_OPERAND_SUFFIX },
-/* address write back, stored in bit 24 */
+/* cache bypass, stored in bit 26 */
#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
- { 'E', 1, 26, ARC_OPERAND_SUFFIX },
+ { 'D', 1, 26, ARC_OPERAND_SUFFIX },
/* unop macro, used to copy REGB to REGC */
#define UNOPMACRO (CACHEBYPASS26 + 1)
{ 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
-/* multiply/shifter detector */
-/* ??? Using ARC_OPERAND_FAKE this way is probably taking things too far. */
-#define MULTSHIFT (UNOPMACRO + 1)
- { 'M', 0, 0, ARC_OPERAND_FAKE, insert_multshift, extract_multshift },
-
/* '.' modifier ('.' required). */
-#define MODDOT (MULTSHIFT + 1)
+#define MODDOT (UNOPMACRO + 1)
{ '.', 1, 0, ARC_MOD_DOT },
/* Dummy 'r' modifier for the register table.
/* end of list place holder */
{ 0 }
};
-
+\f
/* Given a format letter, yields the index into `arc_operands'.
eg: arc_operand_map['a'] = REGA. */
unsigned char arc_operand_map[256];
#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
-/* ARC instructions (sorted by at least the first letter, and equivalent
- opcodes kept together).
-
- By recording the insns this way, the table is not hashable on the opcode.
- That's not a real loss though as there are only a few entries for each
- insn (ld/st being the exception), which are quickly found and since
- they're stored together (eg: all `ld' variants are together) very little
- time is spent on the opcode itself. The slow part is parsing the options,
- but that's always going to be slow.
+/* ARC instructions.
Longer versions of insns must appear before shorter ones (if gas sees
"lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
- junk). */
+ junk). This isn't necessary for `ld' because of the trailing ']'.
+
+ Instructions that are really macros based on other insns must appear
+ before the real insn so they're chosen when disassembling. Eg: The `mov'
+ insn is really the `and' insn.
+
+ This table is best viewed on a wide screen (161 columns). I'd prefer to
+ keep it this way. The rest of the file, however, should be viewable on an
+ 80 column terminal. */
/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
a more general facility for dealing with macros which could be used if
we need to. */
-/* ??? As an experiment, the "mov" macro appears at the start so it is
- prefered to "and" when disassembling. At present, the table needn't be
- sorted, though all opcodes with the same first letter must be kept
- together. */
-const struct arc_opcode arc_opcodes[] = {
- /* Note that "mov" is really an "and". */
+/* This table can't be `const' because members `next_asm' and `next_dis' are
+ computed at run-time. We could split this into two, but that doesn't seem
+ worth it. */
+
+struct arc_opcode arc_opcodes[] = {
+
+ /* Macros appear first. */
+ /* "mov" is really an "and". */
{ "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
- { "mul%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(20) },
- { "mulu%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(21) },
+ /* "asl" is really an "add". */
+ { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ /* "lsl" is really an "add". */
+ { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ /* "nop" is really an "xor". */
+ { "nop", 0xffffffff, 0x7fffffff },
+ /* "rlc" is really an "adc". */
+ { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
+ /* The rest of these needn't be sorted, but it helps to find them if they are. */
{ "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
{ "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
{ "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
- { "asl%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(16) },
- /* Note that "asl" is really an "add". */
- { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
- { "asr%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(18) },
{ "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
{ "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
- { "b%q%.n %B", I(-1), I(4) },
- { "bl%q%.n %B", I(-1), I(5) },
+ { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH },
+ { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH },
{ "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
{ "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
{ "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
/* %Q: force cond_p=1 --> no shimm values */
- { "j%q%Q%.n%.f %b%L", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
+ /* ??? This insn allows an optional flags spec. */
+ { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
/* Put opcode 1 ld insns first so shimm gets prefered over limm. */
/* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "ld%Z%.X%.v%.e %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
- { "ld%Z%.X%.v%.e %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
- { "ld%z%.x%.u%.D %a,[%b,%c]", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
+ { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
+ { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
+ { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
{ "lp%q%.n %B", I(-1), I(6), },
{ "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
- /* Note that "lsl" is really an "add". */
- { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
- { "lsr%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(17) },
{ "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
- /* Note that "nop" is really an "xor". */
- { "nop", 0xffffffff, 0x7fffffff },
{ "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
- /* Note that "rlc" is really an "adc". */
- { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
- { "ror%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(19) },
{ "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
{ "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
{ "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
{ "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
{ "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
- { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
+ { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
/* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "st%y%.w%.E %0%c,[%b]%L", I(-1)+R(-1,25,3)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,3)+R(0,21,1)+R(0,0,511) },
- { "st%y%.w%.E %c,[%b,%d]%S%L", I(-1)+R(-1,25,3)+R(-1,21,1), I(2)+R(0,25,3)+R(0,21,1) },
+ { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
+ { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) },
{ "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
{ "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
};
-int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
+const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
const struct arc_operand_value arc_reg_names[] =
{
to recognize the canonical values. */
{ "r27", 27, REG }, { "r28", 28, REG },
+ /* Someone may wish to refer to these in this way, and it's probably a
+ good idea to reserve them as such anyway. */
+ { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
+
/* Standard auxiliary registers. */
- { "status", 0, AUXREG },
+ { "status", 0, AUXREG },
{ "semaphore", 1, AUXREG },
- { "lp_start", 2, AUXREG },
- { "lp_end", 3, AUXREG },
- { "identity", 4, AUXREG },
- { "debug", 5, AUXREG },
+ { "lp_start", 2, AUXREG },
+ { "lp_end", 3, AUXREG },
+ { "identity", 4, AUXREG },
+ { "debug", 5, AUXREG },
};
-int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
+const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
/* The suffix table.
Operands with the same name must be stored together. */
{ "ls", 14, COND },
{ "pnz", 15, COND },
{ "f", 1, FLAG },
- { "nd", 0, DELAY },
- { "d", 1, DELAY },
- { "jd", 2, DELAY },
-/* { "b", 7, SIZEEXT },*/
-/* { "b", 5, SIZESEX },*/
+ { "nd", ARC_DELAY_NONE, DELAY },
+ { "d", ARC_DELAY_NORMAL, DELAY },
+ { "jd", ARC_DELAY_JUMP, DELAY },
+/*{ "b", 7, SIZEEXT },*/
+/*{ "b", 5, SIZESEX },*/
{ "b", 1, SIZE1 },
{ "b", 1, SIZE10 },
{ "b", 1, SIZE22 },
-/* { "w", 8, SIZEEXT },*/
-/* { "w", 6, SIZESEX },*/
+/*{ "w", 8, SIZEEXT },*/
+/*{ "w", 6, SIZESEX },*/
{ "w", 2, SIZE1 },
{ "w", 2, SIZE10 },
{ "w", 2, SIZE22 },
{ "di", 1, CACHEBYPASS14 },
{ "di", 1, CACHEBYPASS26 },
};
-int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+
+/* Indexed by first letter of opcode. Points to chain of opcodes with same
+ first letter. */
+static struct arc_opcode *opcode_map[26 + 1];
+/* Indexed by insn code. Points to chain of opcodes with same insn code. */
+static struct arc_opcode *icode_map[32];
+\f
/* Configuration flags. */
/* Various ARC_HAVE_XXX bits. */
static int cpu_type;
+/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
+
+int
+arc_get_opcode_mach (bfd_mach, big_p)
+ int bfd_mach, big_p;
+{
+ static int mach_type_map[] =
+ {
+ ARC_MACH_BASE
+ };
+
+ return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
+}
+
/* Initialize any tables that need it.
Must be called once at start up (or when first needed).
- CPU is a set of bits that say what version of the cpu we have. */
+ FLAGS is a set of bits that say what version of the cpu we have,
+ and in particular at least (one of) ARC_MACH_XXX. */
void
-arc_opcode_init_tables (cpu)
- int cpu;
+arc_opcode_init_tables (flags)
+ int flags;
{
- register int i,n;
+ static int init_p = 0;
+
+ cpu_type = flags;
+
+ /* We may be intentionally called more than once (for example gdb will call
+ us each time the user switches cpu). These tables only need to be init'd
+ once though. */
+ /* ??? We can remove the need for arc_opcode_supported by taking it into
+ account here, but I'm not sure I want to do that yet (if ever). */
+ if (!init_p)
+ {
+ register int i,n;
- memset (arc_operand_map, 0, sizeof (arc_operand_map));
- n = sizeof (arc_operands) / sizeof (arc_operands[0]);
- for (i = 0; i < n; i++)
- arc_operand_map[arc_operands[i].fmt] = i;
+ memset (arc_operand_map, 0, sizeof (arc_operand_map));
+ n = sizeof (arc_operands) / sizeof (arc_operands[0]);
+ for (i = 0; i < n; ++i)
+ arc_operand_map[arc_operands[i].fmt] = i;
- cpu_type = cpu;
+ memset (opcode_map, 0, sizeof (opcode_map));
+ memset (icode_map, 0, sizeof (icode_map));
+ /* Scan the table backwards so macros appear at the front. */
+ for (i = arc_opcodes_count - 1; i >= 0; --i)
+ {
+ int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
+ int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
+
+ arc_opcodes[i].next_asm = opcode_map[opcode_hash];
+ opcode_map[opcode_hash] = &arc_opcodes[i];
+
+ arc_opcodes[i].next_dis = icode_map[icode_hash];
+ icode_map[icode_hash] = &arc_opcodes[i];
+ }
+
+ init_p = 1;
+ }
+}
+
+/* Return non-zero if OPCODE is supported on the specified cpu.
+ Cpu selection is made when calling `arc_opcode_init_tables'. */
+
+int
+arc_opcode_supported (opcode)
+ const struct arc_opcode *opcode;
+{
+ if (ARC_OPCODE_CPU (opcode->flags) == 0)
+ return 1;
+ if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
+ return 1;
+ return 0;
+}
+
+/* Return non-zero if OPVAL is supported on the specified cpu.
+ Cpu selection is made when calling `arc_opcode_init_tables'. */
+
+int
+arc_opval_supported (opval)
+ const struct arc_operand_value *opval;
+{
+ if (ARC_OPVAL_CPU (opval->flags) == 0)
+ return 1;
+ if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
+ return 1;
+ return 0;
+}
+
+/* Return the first insn in the chain for assembling INSN. */
+
+const struct arc_opcode *
+arc_opcode_lookup_asm (insn)
+ const char *insn;
+{
+ return opcode_map[ARC_HASH_OPCODE (insn)];
+}
+
+/* Return the first insn in the chain for disassembling INSN. */
+
+const struct arc_opcode *
+arc_opcode_lookup_dis (insn)
+ unsigned int insn;
+{
+ return icode_map[ARC_HASH_ICODE (insn)];
}
\f
/* Nonzero if we've seen an 'f' suffix (in certain insns). */
/* The value of the limm we inserted. Each insn only gets one but it can
appear multiple times. */
static long limm;
+\f
+/* Insertion functions. */
/* Called by the assembler before parsing an instruction. */
{
static char buf[100];
- if (!reg)
+ if (reg == NULL)
{
/* We have a constant that also requires a value stored in a register
field. Handle these by updating the register field and saving the
}
else
{
- *errmsg = "unable to fit different valued constants into instruction";
+ *errmsg = _("unable to fit different valued constants into instruction");
}
}
else
if (reg->type == AUXREG)
{
if (!(mods & ARC_MOD_AUXREG))
- *errmsg = "auxiliary register not allowed here";
+ *errmsg = _("auxiliary register not allowed here");
else
{
insn |= ARC_REG_SHIMM << operand->shift;
/* We should never get an invalid register number here. */
if ((unsigned int) reg->value > 60)
{
- sprintf (buf, "invalid register number `%d'", reg->value);
+ /* xgettext:c-format */
+ sprintf (buf, _("invalid register number `%d'"), reg->value);
*errmsg = buf;
}
else
long value;
const char **errmsg;
{
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ long minval, maxval;
+ static char buf[100];
+
+ if (reg != NULL)
+ {
+ *errmsg = "register appears where shimm value expected";
+ }
+ else
+ {
+ /* This is *way* more general than necessary, but maybe some day it'll
+ be useful. */
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ {
+ minval = -(1 << (operand->bits - 1));
+ maxval = (1 << (operand->bits - 1)) - 1;
+ }
+ else
+ {
+ minval = 0;
+ maxval = (1 << operand->bits) - 1;
+ }
+ if (value < minval || value > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (buf, _("value won't fit in range %ld - %ld"),
+ minval, maxval);
+ *errmsg = buf;
+ }
+ else
+ insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ }
return insn;
}
}
/* Called at the end of processing normal insns (eg: add) to insert a limm
- value (if present) into the insn. Actually, there's nothing for us to do
- as we can't call frag_more, the caller must do that. */
-/* ??? The extract fns take a pointer to two words. The insert insns could be
- converted and then we could do something useful. Not sure it's worth it. */
+ value (if present) into the insn.
+
+ Note that this function is only intended to handle instructions (with 4 byte
+ immediate operands). It is not intended to handle data. */
+
+/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
+ caller must do that. The extract fns take a pointer to two words. The
+ insert fns could be converted and then we could do something useful, but
+ then the reloc handlers would have to know to work on the second word of
+ a 2 word quantity. That's too much so we don't handle them. */
static arc_insn
insert_limmfinish (insn, operand, mods, reg, value, errmsg)
const char **errmsg;
{
if (limm_p)
- ; /* nothing to do */
+ ; /* nothing to do, gas does it */
return insn;
}
long value;
const char **errmsg;
{
- /* FIXME: Addresses are stored * 4. Do we want to handle that here? */
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ if (value & 3)
+ *errmsg = _("branch address not on 4 byte boundary");
+ insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
-/* Fake operand to disallow the multiply and variable shift insns if the cpu
- doesn't have them. */
+/* Insert a limm value as a 26 bit address right shifted 2 into the insn.
+
+ Note that this function is only intended to handle instructions (with 4 byte
+ immediate operands). It is not intended to handle data. */
+
+/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
+ caller must do that. The extract fns take a pointer to two words. The
+ insert fns could be converted and then we could do something useful, but
+ then the reloc handlers would have to know to work on the second word of
+ a 2 word quantity. That's too much so we don't handle them. */
static arc_insn
-insert_multshift (insn, operand, mods, reg, value, errmsg)
+insert_absaddr (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
long value;
const char **errmsg;
{
- if (!(cpu_type & ARC_HAVE_MULT_SHIFT))
- *errmsg = "cpu doesn't support this insn";
+ if (limm_p)
+ ; /* nothing to do */
return insn;
}
\f
{
const struct arc_operand_value *reg = lookup_register (REG, regno);
- if (!reg)
+ if (reg == NULL)
abort ();
- if (opval)
+ if (opval != NULL)
*opval = reg;
value = regno;
}
/* This is really a constant, but tell the caller it has a special
name. */
- if (reg && opval)
+ if (reg != NULL && opval != NULL)
*opval = reg;
}
return 0;
val = arc_opcode_lookup_suffix (operand, 1);
- if (opval && val)
+ if (opval != NULL && val != NULL)
*opval = val;
return val->value;
}
cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
val = arc_opcode_lookup_suffix (operand, cond);
- /* Ignore NULL values of `val'. Several condition code values aren't
- implemented yet. */
- if (opval && val)
+ /* Ignore NULL values of `val'. Several condition code values are
+ reserved for extensions. */
+ if (opval != NULL && val != NULL)
*opval = val;
return cond;
}
-/* The only thing this does is set the `invalid' flag if B != C.
- This is needed because the "mov" macro appears before it's real insn "and"
- and we don't want the disassembler to confuse them. */
+/* Extract a branch address.
+ We return the value as a real address (not right shifted by 2). */
static long
-extract_unopmacro (insn, operand, mods, opval, invalid)
+extract_reladdr (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
- /* ??? This misses the case where B == ARC_REG_SHIMM_UPDATE &&
- C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
- printed as "and"s. */
- if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
- != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
- if (invalid)
- *invalid = 1;
+ long addr;
- return 0;
-}
+ addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ if ((operand->flags & ARC_OPERAND_SIGNED)
+ && (addr & (1 << (operand->bits - 1))))
+ addr -= 1 << operand->bits;
-/* Don't recognize the multiply and variable shift insns if the cpu doesn't
- have them.
+ return addr << 2;
+}
- ??? Actually, we probably should anyway. */
+/* The only thing this does is set the `invalid' flag if B != C.
+ This is needed because the "mov" macro appears before it's real insn "and"
+ and we don't want the disassembler to confuse them. */
static long
-extract_multshift (insn, operand, mods, opval, invalid)
+extract_unopmacro (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
+ /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
+ C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
+ printed as "and"s. */
+ if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
+ != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
+ if (invalid != NULL)
+ *invalid = 1;
+
return 0;
}
projects / deliverable / binutils-gdb.git / blobdiff