[AArch64] Add ARMv8.3 javascript floating-point conversion instruction

[deliverable/binutils-gdb.git] / opcodes / arc-tbl.h

diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 7bda40a9c4e5f2edce2ea1c76f6e95cfd6e78187..3246d8d0e0ac3f68174fa38e802df4582467dcba 100644 (file)
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -3499,6 +3499,9 @@
 /* daddh22<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ.  */
 { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
+/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS.  */
+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
+
 /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
 { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DPX, { RA, RB, RC }, { C_F }},
 
@@ -7763,99 +7766,6 @@
 /* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ.  */
 { "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
 
-/* invld042e  00100RRRRR101110RRRRRRRRRRRRRRRR.  */
-{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f0e  00100RRRRR101111RRRRRRRRRR00111R.  */
-{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f12  00100RRRRR101111RRRRRRRRRR01001R.  */
-{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f14  00100RRRRR101111RRRRRRRRRR0101RR.  */
-{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f18  00100RRRRR101111RRRRRRRRRR011RRR.  */
-{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f20  00100RRRRR101111RRRRRRRRRR10RRRR.  */
-{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f30  00100RRRRR101111RRRRRRRRRR110RRR.  */
-{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f38  00100RRRRR101111RRRRRRRRRR1110RR.  */
-{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f3c  00100RRRRR101111RRRRRRRRRR11110R.  */
-{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f3e  00100RRRRR101111RRRRRRRRRR111110.  */
-{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f3f08  00100RRRRR101111R001RRRRRR111111.  */
-{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f3f10  00100RRRRR101111R01RRRRRRR111111.  */
-{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld042f3f20  00100RRRRR101111R1RRRRRRRR111111.  */
-{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld0506  00101RRRRR00011RRRRRRRRRRRRRRRRR.  */
-{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld050a  00101RRRRR00101RRRRRRRRRRRRRRRRR.  */
-{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld050c  00101RRRRR00110RRRRRRRRRRRRRRRRR.  */
-{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld051e  00101RRRRR01111RRRRRRRRRRRRRRRRR.  */
-{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld0520  00101RRRRR100RRRRRRRRRRRRRRRRRRR.  */
-{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld0528  00101RRRRR1010RRRRRRRRRRRRRRRRRR.  */
-{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052c  00101RRRRR10110RRRRRRRRRRRRRRRRR.  */
-{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052e  00101RRRRR101110RRRRRRRRRRRRRRRR.  */
-{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f02  00101RRRRR101111RRRRRRRRRR00001R.  */
-{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f04  00101RRRRR101111RRRRRRRRRR0001RR.  */
-{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f14  00101RRRRR101111RRRRRRRRRR0101RR.  */
-{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f18  00101RRRRR101111RRRRRRRRRR011RRR.  */
-{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f20  00101RRRRR101111RRRRRRRRRR10RRRR.  */
-{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f30  00101RRRRR101111RRRRRRRRRR110RRR.  */
-{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f38  00101RRRRR101111RRRRRRRRRR1110RR.  */
-{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f3c  00101RRRRR101111RRRRRRRRRR11110R.  */
-{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f3e  00101RRRRR101111RRRRRRRRRR111110.  */
-{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
-/* invld052f3f00  00101RRRRR101111RRRRRRRRRR111111.  */
-{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
 /* j c 00100RRR001000000RRRCCCCCCRRRRRR.  */
 { "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
 
@@ -12985,22 +12895,22 @@
 { "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }},
 
 /* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110.  */
-{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
 
 /* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110.  */
-{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
 
 /* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110.  */
-{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
 
 /* prealloc limm,c 00100110RR1100010111CCCCCC111110.  */
-{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
 
 /* prealloc limm 000101100000000001110RR001111110.  */
-{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
 
 /* prealloc limm,s9 00010110ssssssssS1110RR001111110.  */
-{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
 
 /* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110.  */
 { "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
@@ -18061,64 +17971,64 @@
 { "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }},
 
 /* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA.  */
-{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
+{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
 
 /* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110.  */
-{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
+{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
 
 /* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ.  */
-{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
 
 /* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA.  */
-{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110.  */
-{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ.  */
-{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
 
 /* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS.  */
-{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
 
 /* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA.  */
-{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
+{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
 
 /* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA.  */
-{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
+{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
 
 /* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110.  */
-{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
+{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
 
 /* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110.  */
-{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
 
 /* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ.  */
-{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
 
 /* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ.  */
-{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
 
 /* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA.  */
-{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110.  */
-{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ.  */
-{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
 
 /* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS.  */
-{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
 
 /* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA.  */
-{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
 
 /* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110.  */
-{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
 
 /* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ.  */
-{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA.  */
 { "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},