various i386-aout and i386-coff target removal

[deliverable/binutils-gdb.git] / opcodes / arm-dis.c

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index d5a20cb888ca2beed575ee168fc554c8f4a36d68..6f93cfd25bdb9d8af4a7bf8cfef55ee835795428 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the ARM
-   Copyright (C) 1994-2017 Free Software Foundation, Inc.
+   Copyright (C) 1994-2018 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
@@ -1901,6 +1901,9 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
 
+  /* CSDB.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
+
   /* ARM V6K NOP hints.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     0x0320f001, 0x0fffffff, "yield%c"},
@@ -2527,7 +2530,7 @@ static const struct opcode16 thumb_opcodes[] =
 
   /* ARMv8-M Security Extensions instructions.  */
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
-  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
 
   /* ARM V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
@@ -2819,6 +2822,9 @@ static const struct opcode32 thumb32_opcodes[] =
   /* Security extension instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
 
+  /* CSDB.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
+
   /* Instructions defined in the basic V6T2 set.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
@@ -3387,7 +3393,7 @@ print_insn_coprocessor (bfd_vma pc,
   struct arm_private_data *private_data = info->private_data;
   arm_feature_set allowed_arches = ARM_ARCH_NONE;
 
-  ARM_FEATURE_COPY (allowed_arches, private_data->features);
+  allowed_arches = private_data->features;
 
   for (insn = coprocessor_opcodes; insn->assembler; insn++)
     {
@@ -3413,7 +3419,7 @@ print_insn_coprocessor (bfd_vma pc,
            continue;
 
          case SENTINEL_GENERIC_START:
-           ARM_FEATURE_COPY (allowed_arches, private_data->features);
+           allowed_arches = private_data->features;
            continue;
 
          default:
@@ -6139,14 +6145,17 @@ parse_arm_disassembler_options (const char *options)
              }
 
          if (i >= NUM_ARM_OPTIONS)
-           fprintf (stderr, _("Unrecognised register name set: %s\n"), opt);
+           /* xgettext: c-format */
+           opcodes_error_handler (_("unrecognised register name set: %s"),
+                                  opt);
        }
       else if (CONST_STRNEQ (opt, "force-thumb"))
        force_thumb = 1;
       else if (CONST_STRNEQ (opt, "no-force-thumb"))
        force_thumb = 0;
       else
-       fprintf (stderr, _("Unrecognised disassembler option: %s\n"), opt);
+       /* xgettext: c-format */
+       opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
     }
 
   return;