Replace solib_global_lookup with gdbarch_iterate_over_objfiles_in_search_order

[deliverable/binutils-gdb.git] / opcodes / arm-dis.c

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 033725dbad99fb93f8f9506a32f0f55c63b2ae42..8ff86bf4d62ff69ed9a4a5f3f5bc5c81b3abbe85 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2073,6 +2073,7 @@ static const struct opcode32 neon_opcodes[] =
    %u                  print 'U' (unsigned) or 'S' for various mve instructions
    %i                  print MVE predicate(s) for vpt and vpst
    %j                  print a 5-bit immediate from hw2[14:12,7:6]
+   %k                  print 48 if the 7th position bit is set else print 64.
    %m                  print rounding mode for vcvt and vrint
    %n                  print vector comparison code for predicated instruction
    %s                  print size for various vcvt instructions
@@ -2950,6 +2951,16 @@ static const struct mopcode32 mve_opcodes[] =
    0xef200150, 0xffb11f51,
    "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
 
+  /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
+     "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
+     MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
+     array.  */
+
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VMOV_VEC_TO_VEC,
+   0xef200150, 0xffb11f51,
+   "vmov%v\t%13-15,22Q, %17-19,7Q"},
+
   /* Vector VQDMULL T1 variant.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VQDMULL_T1,
@@ -3373,8 +3384,8 @@ static const struct mopcode32 mve_opcodes[] =
 
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_SQRSHRL,
-   0xea51012d, 0xfff101ff,
-   "sqrshrl%c\t%17-19l, %9-11h, %12-15S"},
+   0xea51012d, 0xfff1017f,
+   "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
 
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_SQRSHR,
@@ -3403,8 +3414,8 @@ static const struct mopcode32 mve_opcodes[] =
 
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_UQRSHLL,
-   0xea51010d, 0xfff101ff,
-   "uqrshll%c\t%17-19l, %9-11h, %12-15S"},
+   0xea51010d, 0xfff1017f,
+   "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
 
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_UQRSHL,
@@ -6103,6 +6114,12 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       else
        return FALSE;
 
+    case MVE_VMOV_VEC_TO_VEC:
+      if ((arm_decode_field (given, 5, 5) == 1)
+         || (arm_decode_field (given, 22, 22) == 1))
+         return TRUE;
+      return FALSE;
+
     case MVE_VMOV_IMM_TO_VEC:
       if (arm_decode_field (given, 5, 5) == 0)
       {
@@ -9213,6 +9230,13 @@ print_insn_mve (struct disassemble_info *info, long given)
          if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
            is_undefined = TRUE;
 
+         /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
+            i.e "VMOV Qd, Qm".  */
+         if ((insn->mve_op == MVE_VORR_REG)
+             && (arm_decode_field (given, 1, 3)
+                 == arm_decode_field (given, 17, 19)))
+           continue;
+
          for (c = insn->assembler; *c; c++)
            {
              if (*c == '%')
@@ -9254,6 +9278,11 @@ print_insn_mve (struct disassemble_info *info, long given)
                      }
                      break;
 
+                   case 'k':
+                     func (stream, "#%u",
+                           (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
+                     break;
+
                    case 'n':
                      print_vec_condition (info, given, insn->mve_op);
                      break;