{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+ /* ARMv8-M Mainline Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
+
/* Register load/store. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
"%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
/* V8.2 RAS extension instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
0xe320f010, 0xffffffff, "esb"},
/* V8 instructions. */
{
/* Thumb instructions. */
+ /* ARMv8-M Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
+
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
- /* V8-M instructions. */
+ /* ARMv8-M and ARMv8-M Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+ 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+ 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
/* ARM V8.2 RAS extension instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
0xf3af8010, 0xffffffff, "esb"},
/* V8 instructions. */
{
switch (regno)
{
- case 0: return "APSR";
- case 1: return "IAPSR";
- case 2: return "EAPSR";
- case 3: return "PSR";
- case 5: return "IPSR";
- case 6: return "EPSR";
- case 7: return "IEPSR";
- case 8: return "MSP";
- case 9: return "PSP";
- case 16: return "PRIMASK";
- case 17: return "BASEPRI";
- case 18: return "BASEPRI_MAX";
- case 19: return "FAULTMASK";
- case 20: return "CONTROL";
+ case 0x0: return "APSR";
+ case 0x1: return "IAPSR";
+ case 0x2: return "EAPSR";
+ case 0x3: return "PSR";
+ case 0x5: return "IPSR";
+ case 0x6: return "EPSR";
+ case 0x7: return "IEPSR";
+ case 0x8: return "MSP";
+ case 0x9: return "PSP";
+ case 0xa: return "MSPLIM";
+ case 0xb: return "PSPLIM";
+ case 0x10: return "PRIMASK";
+ case 0x11: return "BASEPRI";
+ case 0x12: return "BASEPRI_MAX";
+ case 0x13: return "FAULTMASK";
+ case 0x14: return "CONTROL";
+ case 0x88: return "MSP_NS";
+ case 0x89: return "PSP_NS";
+ case 0x8a: return "MSPLIM_NS";
+ case 0x8b: return "PSPLIM_NS";
+ case 0x90: return "PRIMASK_NS";
+ case 0x91: return "BASEPRI_NS";
+ case 0x93: return "FAULTMASK_NS";
+ case 0x94: return "CONTROL_NS";
+ case 0x98: return "SP_NS";
default: return "<unknown>";
}
}
/* If the symbol has function type then use that. */
if (type == STT_FUNC || type == STT_GNU_IFUNC)
{
- if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
+ if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
+ == ST_BRANCH_TO_THUMB)
*map_type = MAP_THUMB;
else
*map_type = MAP_ARM;
we finished last time. */
/* PR 14006. When the address is 0 we are either at the start of the
very first function, or else the first function in a new, unlinked
- executable section (eg because uf -ffunction-sections). Either way
+ executable section (eg because of -ffunction-sections). Either way
start scanning from the beginning of the symbol table, not where we
left off last time. */
if (pc == 0)
es = *(elf_symbol_type **)(info->symbols);
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
- is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
- == ST_BRANCH_TO_THUMB)
- || type == STT_ARM_16BIT);
+ is_thumb =
+ ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
+ == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
}
else if (bfd_asymbol_flavour (*info->symbols)
== bfd_target_mach_o_flavour)