/* Disassemble ADI Blackfin Instructions.
- Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
+ Free Software Foundation, Inc.
This file is part of libopcodes.
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
+#include "sysdep.h"
#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
#include "opcode/bfin.h"
-#define M_S2RND 1
-#define M_T 2
-#define M_W32 3
-#define M_FU 4
-#define M_TFU 6
-#define M_IS 8
-#define M_ISS2 9
-#define M_IH 11
-#define M_IU 12
-
#ifndef PRINTF
#define PRINTF printf
#endif
if (constant_formats[cf].pcrel)
ea += pc;
- /* truncate to 32-bits for proper symbol lookup/matching */
- ea = (bu32)ea;
+ /* truncate to 32-bits for proper symbol lookup/matching */
+ ea = (bu32)ea;
- if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
- {
+ if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
+ {
outf->print_address_func (ea, outf);
return "";
- }
- else
- {
+ }
+ else
+ {
sprintf (buf, "%lx", (unsigned long) x);
return buf;
- }
+ }
}
/* Negative constants have an implied sign bit. */
x <<= constant_formats[cf].scale;
if (constant_formats[cf].decimal)
- {
- if (constant_formats[cf].leading)
- {
- char ps[10];
- sprintf (ps, "%%%ii", constant_formats[cf].leading);
- sprintf (buf, ps, x);
- }
- else
- sprintf (buf, "%li", x);
- }
+ sprintf (buf, "%*li", constant_formats[cf].leading, x);
else
{
if (constant_formats[cf].issigned && x < 0)
REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
REG_AQ, REG_V, REG_VS,
REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
- REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
+ REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
LIM_REG_CLASSES
};
-static const char *reg_names[] =
+static const char * const reg_names[] =
{
"R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
"R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
"AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
"AQ", "V", "VS",
"sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
- "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
+ "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
"CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
"RETE", "EMUDAT",
"R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
/* RL(0..7). */
-static enum machine_registers decode_dregs_lo[] =
+static const enum machine_registers decode_dregs_lo[] =
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
};
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
/* RH(0..7). */
-static enum machine_registers decode_dregs_hi[] =
+static const enum machine_registers decode_dregs_hi[] =
{
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
};
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
/* R(0..7). */
-static enum machine_registers decode_dregs[] =
+static const enum machine_registers decode_dregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
};
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
/* R BYTE(0..7). */
-static enum machine_registers decode_dregs_byte[] =
+static const enum machine_registers decode_dregs_byte[] =
{
REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
};
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
/* P(0..5) SP FP. */
-static enum machine_registers decode_pregs[] =
+static const enum machine_registers decode_pregs[] =
{
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
#define pregs(x) REGNAME (decode_pregs[(x) & 7])
#define spfp(x) REGNAME (decode_spfp[(x) & 1])
-#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
+#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
#define accum(x) REGNAME (decode_accum[(x) & 1])
/* I(0..3). */
-static enum machine_registers decode_iregs[] =
+static const enum machine_registers decode_iregs[] =
{
REG_I0, REG_I1, REG_I2, REG_I3,
};
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
/* M(0..3). */
-static enum machine_registers decode_mregs[] =
+static const enum machine_registers decode_mregs[] =
{
REG_M0, REG_M1, REG_M2, REG_M3,
};
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
/* dregs pregs. */
-static enum machine_registers decode_dpregs[] =
+static const enum machine_registers decode_dpregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
/* [dregs pregs]. */
-static enum machine_registers decode_gregs[] =
+static const enum machine_registers decode_gregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
};
-#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
+#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs)]. */
-static enum machine_registers decode_regs[] =
+static const enum machine_registers decode_regs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
};
-#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
+#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
-static enum machine_registers decode_regs_lo[] =
+static const enum machine_registers decode_regs_lo[] =
{
REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
};
-#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
+#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
+
/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
-static enum machine_registers decode_regs_hi[] =
+static const enum machine_registers decode_regs_hi[] =
{
REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
};
-#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
+#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
-static enum machine_registers decode_statbits[] =
+static const enum machine_registers decode_statbits[] =
{
REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
#define statbits(x) REGNAME (decode_statbits[(x) & 31])
/* LC0 LC1. */
-static enum machine_registers decode_counters[] =
+static const enum machine_registers decode_counters[] =
{
REG_LC0, REG_LC1,
};
/* [dregs pregs (iregs mregs) (bregs lregs)
dregs2_sysregs1 open sysregs2 sysregs3]. */
-static enum machine_registers decode_allregs[] =
+static const enum machine_registers decode_allregs[] =
{
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
- REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
+ REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
#define allreg(r,g) (!IS_RESERVEDREG (g, r))
#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
-#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
+#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
/* (arch.pm)arch_disassembler_functions. */
#ifndef OUTS
-#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
+#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
#endif
static void
}
static int
-decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
+decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
{
const char *s0, *s1;
}
static int
-decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
+decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
{
const char *a;
const char *sop = "<unknown op>";
OUTS (outf, ")");
}
-struct saved_state
+static struct saved_state
{
bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
- bu32 a0x, a0w, a1x, a1w;
+ bu32 ax[2], aw[2];
bu32 lt[2], lc[2], lb[2];
- int ac0, ac0_copy, ac1, an, aq;
- int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
- int rnd_mod;
- int v_internal;
- bu32 pc, rets;
-
- int ticks;
- int insts;
-
- int exception;
-
- int end_of_registers;
-
- int msize;
- unsigned char *memory;
- unsigned long bfd_mach;
-} saved_state;
+ bu32 rets;
+} saved_state;
#define DREG(x) (saved_state.dpregs[x])
-#define GREG(x,i) DPREG ((x) | (i << 3))
+#define GREG(x, i) DPREG ((x) | ((i) << 3))
#define DPREG(x) (saved_state.dpregs[x])
#define DREG(x) (saved_state.dpregs[x])
-#define PREG(x) (saved_state.dpregs[x + 8])
+#define PREG(x) (saved_state.dpregs[(x) + 8])
#define SPREG PREG (6)
#define FPREG PREG (7)
#define IREG(x) (saved_state.iregs[x])
#define MREG(x) (saved_state.mregs[x])
#define BREG(x) (saved_state.bregs[x])
#define LREG(x) (saved_state.lregs[x])
-#define A0XREG (saved_state.a0x)
-#define A0WREG (saved_state.a0w)
-#define A1XREG (saved_state.a1x)
-#define A1WREG (saved_state.a1w)
-#define CCREG (saved_state.cc)
-#define LC0REG (saved_state.lc[0])
-#define LT0REG (saved_state.lt[0])
-#define LB0REG (saved_state.lb[0])
-#define LC1REG (saved_state.lc[1])
-#define LT1REG (saved_state.lt[1])
-#define LB1REG (saved_state.lb[1])
+#define AXREG(x) (saved_state.ax[x])
+#define AWREG(x) (saved_state.aw[x])
+#define LCREG(x) (saved_state.lc[x])
+#define LTREG(x) (saved_state.lt[x])
+#define LBREG(x) (saved_state.lb[x])
#define RETSREG (saved_state.rets)
-#define PCREG (saved_state.pc)
static bu32 *
get_allreg (int grp, int reg)
REG_LASTREG */
switch (fullreg >> 2)
{
- case 0: case 1: return &DREG (reg); break;
- case 2: case 3: return &PREG (reg); break;
- case 4: return &IREG (reg & 3); break;
- case 5: return &MREG (reg & 3); break;
- case 6: return &BREG (reg & 3); break;
- case 7: return &LREG (reg & 3); break;
+ case 0: case 1: return &DREG (reg);
+ case 2: case 3: return &PREG (reg);
+ case 4: return &IREG (reg & 3);
+ case 5: return &MREG (reg & 3);
+ case 6: return &BREG (reg & 3);
+ case 7: return &LREG (reg & 3);
default:
switch (fullreg)
{
- case 32: return &saved_state.a0x;
- case 33: return &saved_state.a0w;
- case 34: return &saved_state.a1x;
- case 35: return &saved_state.a1w;
- case 39: return &saved_state.rets;
- case 48: return &LC0REG;
- case 49: return <0REG;
- case 50: return &LB0REG;
- case 51: return &LC1REG;
- case 52: return <1REG;
- case 53: return &LB1REG;
+ case 32: return &AXREG (0);
+ case 33: return &AWREG (0);
+ case 34: return &AXREG (1);
+ case 35: return &AWREG (1);
+ case 39: return &RETSREG;
+ case 48: return &LCREG (0);
+ case 49: return <REG (0);
+ case 50: return &LBREG (0);
+ case 51: return &LCREG (1);
+ case 52: return <REG (1);
+ case 53: return &LBREG (1);
}
- return 0;
}
+ abort ();
}
static int
int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
- /* Reserved slots cannot be a src/dst. */
+ /* Reserved slots cannot be a src/dst. */
if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
goto invalid_move;
else
return 0;
- if (! parallel )
- {
- OUTS (outf, ";\t\t/* ( ");
- if (op == 0 || op == 1)
- OUTS (outf, "2");
- else if (op == 2 || op == 3)
+ if (! parallel)
+ {
+ OUTS (outf, ";\t\t/* ( ");
+ if (op == 0 || op == 1)
+ OUTS (outf, "2");
+ else if (op == 2 || op == 3)
OUTS (outf, "4");
- OUTS (outf, ") */");
- comment = 1;
- }
+ OUTS (outf, ") */");
+ comment = 1;
+ }
return 2;
}
if (parallel)
return 0;
+ if (reg > 7)
+ return 0;
+
if (rop == 0)
{
OUTS (outf, "LSETUP");
OUTS (outf, " (X)");
}
else if (H == 0 && S == 1 && Z == 0)
- {
+ {
OUTS (outf, regs (reg, grp));
OUTS (outf, " = ");
OUTS (outf, imm16 (hword));
}
if (S == 1 || Z == 1)
{
- OUTS (outf, ";\t\t/*\t\t");
- OUTS (outf, regs (reg, grp));
- OUTS (outf, "=0x");
- OUTS (outf, huimm32e (*pval));
- OUTS (outf, "(");
- OUTS (outf, imm32 (*pval));
- OUTS (outf, ") */");
- comment = 1;
+ OUTS (outf, ";\t\t/*\t\t");
+ OUTS (outf, regs (reg, grp));
+ OUTS (outf, "=0x");
+ OUTS (outf, huimm32e (*pval));
+ OUTS (outf, "(");
+ OUTS (outf, imm32 (*pval));
+ OUTS (outf, ") */");
+ comment = 1;
}
return 4;
}
{
if (MM)
OUTS (outf, " (M)");
- MM = 0;
OUTS (outf, ", ");
}
}
if (w0 == 1 || op0 != 3)
{
+ /* Clear MM option since it only matters for MAC1, and if we made
+ it this far, we've already shown it or we want to ignore it. */
+ MM = 0;
+
if (w0)
OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
if (w1)
{
- OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
+ OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
OUTS (outf, " = ");
decode_multfunc (h01, h11, src0, src1, outf);
if (w0)
{
- OUTS (outf, dregs (dst));
+ OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
OUTS (outf, " = ");
decode_multfunc (h00, h10, src0, src1, outf);
}
else if (aop == 3 && aopcde == 11 && s == 1)
OUTS (outf, "A0 -= A1 (W32)");
- else if (aop == 3 && aopcde == 22 && HL == 1)
- {
- OUTS (outf, dregs (dst0));
- OUTS (outf, " = BYTEOP2M (");
- OUTS (outf, dregs (src0 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src0));
- OUTS (outf, ", ");
- OUTS (outf, dregs (src1 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src1));
- OUTS (outf, ") (TH");
- if (s == 1)
- OUTS (outf, ", R)");
- else
- OUTS (outf, ")");
- }
- else if (aop == 3 && aopcde == 22 && HL == 0)
- {
- OUTS (outf, dregs (dst0));
- OUTS (outf, " = BYTEOP2M (");
- OUTS (outf, dregs (src0 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src0));
- OUTS (outf, ", ");
- OUTS (outf, dregs (src1 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src1));
- OUTS (outf, ") (TL");
- if (s == 1)
- OUTS (outf, ", R)");
- else
- OUTS (outf, ")");
- }
- else if (aop == 2 && aopcde == 22 && HL == 1)
- {
- OUTS (outf, dregs (dst0));
- OUTS (outf, " = BYTEOP2M (");
- OUTS (outf, dregs (src0 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src0));
- OUTS (outf, ", ");
- OUTS (outf, dregs (src1 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src1));
- OUTS (outf, ") (RNDH");
- if (s == 1)
- OUTS (outf, ", R)");
- else
- OUTS (outf, ")");
- }
- else if (aop == 2 && aopcde == 22 && HL == 0)
- {
- OUTS (outf, dregs (dst0));
- OUTS (outf, " = BYTEOP2M (");
- OUTS (outf, dregs (src0 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src0));
- OUTS (outf, ", ");
- OUTS (outf, dregs (src1 + 1));
- OUTS (outf, ":");
- OUTS (outf, imm5d (src1));
- OUTS (outf, ") (RNDL");
- if (s == 1)
- OUTS (outf, ", R)");
- else
- OUTS (outf, ")");
- }
else if (aop == 1 && aopcde == 22 && HL == 1)
{
OUTS (outf, dregs (dst0));
OUTS (outf, " = (A0 += A1)");
}
else if (aop == 3 && HL == 0 && aopcde == 16)
- OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
+ OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
else if (aop == 0 && aopcde == 23 && HL == 1)
{
int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
-
if (sop == 0 && sopcde == 0)
{
OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
}
else if (fn == 1)
{
- OUTS (outf, "PRNT");
+ OUTS (outf, "PRNT ");
OUTS (outf, allregs (reg, grp));
}
else
{
if (parallel)
{
- OUTS (outf, "ILLEGAL");
- return 0;
+ OUTS (outf, "ILLEGAL");
+ return 0;
}
OUTS (outf, "MNOP");
return 4;
return rv;
}
-
int
print_insn_bfin (bfd_vma pc, disassemble_info *outf)
{
int len;
parallel = 1;
- outf->fprintf_func (outf->stream, " || ");
+ OUTS (outf, " || ");
len = _print_insn_bfin (pc + 4, outf);
- outf->fprintf_func (outf->stream, " || ");
+ OUTS (outf, " || ");
if (len != 2)
- legal = 0;
+ legal = 0;
len = _print_insn_bfin (pc + 6, outf);
if (len != 2)
legal = 0;
count = 8;
else
{
- outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
+ OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
comment = 1;
count = 0;
}
}
if (!comment)
- outf->fprintf_func (outf->stream, ";");
+ OUTS (outf, ";");
if (count == 0)
return 2;
projects / deliverable / binutils-gdb.git / blobdiff